*\r
***************************************************************/\r
\r
+ CC1120_SYNC3, 0xD3, /* Sync Word Configuration [31:24] */\r
+ CC1120_SYNC2, 0x91, /* Sync Word Configuration [23:16] */\r
+ CC1120_SYNC1, 0xD3, /* Sync Word Configuration [15:8] */\r
+ CC1120_SYNC0, 0x91, /* Sync Word Configuration [7:0] */\r
\r
- CC1120_SYNC3, 0x93, /* Sync Word Configuration [31:24] */\r
- CC1120_SYNC2, 0x0b, /* Sync Word Configuration [23:16] */\r
- CC1120_SYNC1, 0x51, /* Sync Word Configuration [15:8] */\r
- CC1120_SYNC0, 0xde, /* Sync Word Configuration [7:0] */\r
- CC1120_SYNC_CFG1, 0x08, /* Sync Word Detection Configuration */\r
- CC1120_SYNC_CFG0, 0x17, /* Sync Word Length Configuration */\r
- CC1120_DEVIATION_M, 0x50, /* Frequency Deviation Configuration */\r
- CC1120_MODCFG_DEV_E, 0x0d, /* Modulation Format and Frequency Deviation Configuration */\r
+ CC1120_SYNC_CFG1, /* Sync Word Detection Configuration */\r
+ (CC1120_SYNC_CFG1_DEM_CFG_PQT_GATING_ENABLED << CC1120_SYNC_CFG1_DEM_CFG) |\r
+ (0x07 << CC1120_SYNC_CFG1_SYNC_THR),\r
+ CC1120_SYNC_CFG0,\r
+ (CC1120_SYNC_CFG0_SYNC_MODE_16_BITS << CC1120_SYNC_CFG0_SYNC_MODE) |\r
+ (CC1120_SYNC_CFG0_SYNC_NUM_ERROR_2 << CC1120_SYNC_CFG0_SYNC_NUM_ERROR),\r
CC1120_DCFILT_CFG, 0x1c, /* Digital DC Removal Configuration */\r
- CC1120_PREAMBLE_CFG1, 0x18, /* Preamble Length Configuration */\r
- CC1120_PREAMBLE_CFG0, 0x2a, /* */\r
+ CC1120_PREAMBLE_CFG1, /* Preamble Length Configuration */\r
+ (CC1120_PREAMBLE_CFG1_NUM_PREAMBLE_4_BYTES << CC1120_PREAMBLE_CFG1_NUM_PREAMBLE) |\r
+ (CC1120_PREAMBLE_CFG1_PREAMBLE_WORD_AA << CC1120_PREAMBLE_CFG1_PREAMBLE_WORD),\r
+ CC1120_PREAMBLE_CFG0,\r
+ (1 << CC1120_PREAMBLE_CFG0_PQT_EN) |\r
+ (0x6 << CC1120_PREAMBLE_CFG0_PQT),\r
CC1120_FREQ_IF_CFG, 0x40, /* RX Mixer Frequency Configuration */\r
CC1120_IQIC, 0x46, /* Digital Image Channel Compensation Configuration */\r
CC1120_CHAN_BW, 0x02, /* Channel Filter Configuration */\r
- CC1120_MDMCFG1, 0x46, /* General Modem Parameter Configuration */\r
+\r
+ CC1120_MDMCFG1, /* General Modem Parameter Configuration */\r
+ (0 << CC1120_MDMCFG1_CARRIER_SENSE_GATE) |\r
+ (1 << CC1120_MDMCFG1_FIFO_EN) |\r
+ (0 << CC1120_MDMCFG1_MANCHESTER_EN) |\r
+ (0 << CC1120_MDMCFG1_INVERT_DATA_EN) |\r
+ (0 << CC1120_MDMCFG1_COLLISION_DETECT_EN) |\r
+ (CC1120_MDMCFG1_DVGA_GAIN_9 << CC1120_MDMCFG1_DVGA_GAIN) |\r
+ (0 << CC1120_MDMCFG1_SINGLE_ADC_EN),\r
CC1120_MDMCFG0, 0x05, /* General Modem Parameter Configuration */\r
- CC1120_DRATE2, 0x93, /* Data Rate Configuration Exponent and Mantissa [19:16] */\r
- CC1120_DRATE1, 0xa4, /* Data Rate Configuration Mantissa [15:8] */\r
- CC1120_DRATE0, 0x00, /* Data Rate Configuration Mantissa [7:0] */\r
+\r
CC1120_AGC_REF, 0x20, /* AGC Reference Level Configuration */\r
CC1120_AGC_CS_THR, 0x19, /* Carrier Sense Threshold Configuration */\r
CC1120_AGC_GAIN_ADJUST, 0x00, /* RSSI Offset Configuration */\r
CC1120_AGC_CFG2, 0x20, /* AGC Configuration */\r
CC1120_AGC_CFG1, 0xa9, /* AGC Configuration */\r
CC1120_AGC_CFG0, 0xcf, /* AGC Configuration */\r
- CC1120_FIFO_CFG, 0x00, /* FIFO Configuration */\r
+ CC1120_FIFO_CFG, /* FIFO Configuration */\r
+ (0 << CC1120_FIFO_CFG_CRC_AUTOFLUSH) |\r
+ (0x40 << CC1120_FIFO_CFG_FIFO_THR),\r
CC1120_DEV_ADDR, 0x00, /* Device Address Configuration */\r
- CC1120_SETTLING_CFG, 0x03, /* Frequency Synthesizer Calibration and Settling Configuration */\r
- CC1120_FS_CFG, 0x14, /* Frequency Synthesizer Configuration */\r
+ CC1120_SETTLING_CFG, /* Frequency Synthesizer Calibration and Settling Configuration */\r
+ (CC1120_SETTLING_CFG_FS_AUTOCAL_IDLE_TO_ON << CC1120_SETTLING_CFG_FS_AUTOCAL) |\r
+ (CC1120_SETTLING_CFG_LOCK_TIME_50_20 << CC1120_SETTLING_CFG_LOCK_TIME) |\r
+ (CC1120_SETTLING_CFG_FSREG_TIME_60 << CC1120_SETTLING_CFG_FSREG_TIME),\r
+ CC1120_FS_CFG, /* Frequency Synthesizer Configuration */\r
+ (1 << CC1120_FS_CFG_LOCK_EN) |\r
+ (CC1120_FS_CFG_FSD_BANDSELECT_410_480 << CC1120_FS_CFG_FSD_BANDSELECT),\r
CC1120_WOR_CFG1, 0x08, /* eWOR Configuration, Reg 1 */\r
CC1120_WOR_CFG0, 0x21, /* eWOR Configuration, Reg 0 */\r
CC1120_WOR_EVENT0_MSB, 0x00, /* Event 0 Configuration */\r
CC1120_WOR_EVENT0_LSB, 0x00, /* Event 0 Configuration */\r
+#if 0\r
CC1120_PKT_CFG2, 0x04, /* Packet Configuration, Reg 2 */\r
CC1120_PKT_CFG1, 0x45, /* Packet Configuration, Reg 1 */\r
- CC1120_PKT_CFG0, 0x20, /* Packet Configuration, Reg 0 */\r
+ CC1120_PKT_CFG0, 0x00, /* Packet Configuration, Reg 0 */\r
+#endif\r
CC1120_RFEND_CFG1, 0x0f, /* RFEND Configuration, Reg 1 */\r
CC1120_RFEND_CFG0, 0x00, /* RFEND Configuration, Reg 0 */\r
- CC1120_PA_CFG2, 0x3f, /* Power Amplifier Configuration, Reg 2 */\r
+ // CC1120_PA_CFG2, 0x3f, /* Power Amplifier Configuration, Reg 2 */\r
+ CC1120_PA_CFG2, 0x3f, /* Power Amplifier Configuration, Reg 2 */\r
CC1120_PA_CFG1, 0x56, /* Power Amplifier Configuration, Reg 1 */\r
CC1120_PA_CFG0, 0x7b, /* Power Amplifier Configuration, Reg 0 */\r
CC1120_PKT_LEN, 0xff, /* Packet Length Configuration */\r
CC1120_MARC_SPARE, 0x00, /* MARC Spare */\r
CC1120_ECG_CFG, 0x00, /* External Clock Frequency Configuration */\r
CC1120_SOFT_TX_DATA_CFG, 0x00, /* Soft TX Data Configuration */\r
- CC1120_EXT_CTRL, 0x01, /* External Control Configuration */\r
+ CC1120_EXT_CTRL, 0x00, /* External Control Configuration */\r
CC1120_RCCAL_FINE, 0x00, /* RC Oscillator Calibration (fine) */\r
CC1120_RCCAL_COARSE, 0x00, /* RC Oscillator Calibration (coarse) */\r
CC1120_RCCAL_OFFSET, 0x00, /* RC Oscillator Calibration Clock Offset */\r
CC1120_FREQOFF1, 0x00, /* Frequency Offset (MSB) */\r
CC1120_FREQOFF0, 0x00, /* Frequency Offset (LSB) */\r
- CC1120_FREQ2, 0x6c, /* Frequency Configuration [23:16] */\r
- CC1120_FREQ1, 0xa3, /* Frequency Configuration [15:8] */\r
- CC1120_FREQ0, 0x33, /* Frequency Configuration [7:0] */\r
CC1120_IF_ADC2, 0x02, /* Analog to Digital Converter Configuration, Reg 2 */\r
CC1120_IF_ADC1, 0xa6, /* Analog to Digital Converter Configuration, Reg 1 */\r
CC1120_IF_ADC0, 0x04, /* Analog to Digital Converter Configuration, Reg 0 */\r
projects / fw / altos / blobdiff