#include <ao.h>
#include <ao_cc1120.h>
#include <ao_exti.h>
+#include <ao_fec.h>
-uint8_t ao_radio_done;
+uint8_t ao_radio_wake;
uint8_t ao_radio_mutex;
uint8_t ao_radio_abort;
#define CC1120_DEBUG 1
+#define CC1120_TRACE 0
-uint32_t ao_radio_cal = 1186611;
+uint32_t ao_radio_cal = 0x6ca333;
+
+#define FOSC 32000000
#define ao_radio_select() ao_spi_get_mask(AO_CC1120_SPI_CS_PORT,(1 << AO_CC1120_SPI_CS_PIN),AO_CC1120_SPI_BUS)
#define ao_radio_deselect() ao_spi_put_mask(AO_CC1120_SPI_CS_PORT,(1 << AO_CC1120_SPI_CS_PIN),AO_CC1120_SPI_BUS)
uint8_t data[2];
uint8_t d;
-#if CC1120_DEBUG
- printf("ao_radio_reg_read (%04x): ", addr); flush();
+#if CC1120_TRACE
+ printf("\t\tao_radio_reg_read (%04x): ", addr); flush();
#endif
if (CC1120_IS_EXTENDED(addr)) {
data[0] = ((1 << CC1120_READ) |
ao_radio_spi_send(data, d);
ao_radio_spi_recv(data, 1);
ao_radio_deselect();
-#if CC1120_DEBUG
+#if CC1120_TRACE
printf (" %02x\n", data[0]);
#endif
return data[0];
uint8_t data[3];
uint8_t d;
-#if CC1120_DEBUG
- printf("ao_radio_reg_write (%04x): %02x\n", addr, value);
+#if CC1120_TRACE
+ printf("\t\tao_radio_reg_write (%04x): %02x\n", addr, value);
#endif
if (CC1120_IS_EXTENDED(addr)) {
- data[0] = ((1 << CC1120_READ) |
+ data[0] = ((0 << CC1120_READ) |
(0 << CC1120_BURST) |
CC1120_EXTENDED);
data[1] = addr;
d = 2;
} else {
- data[0] = ((1 << CC1120_READ) |
+ data[0] = ((0 << CC1120_READ) |
(0 << CC1120_BURST) |
addr);
d = 1;
{
uint8_t in;
+#if CC1120_TRACE
+ printf("\t\tao_radio_strobe (%02x): ", addr); flush();
+#endif
ao_radio_select();
ao_radio_duplex(&addr, &in, 1);
ao_radio_deselect();
+#if CC1120_TRACE
+ printf("%02x\n", in); flush();
+#endif
return in;
}
ao_radio_recv_abort(void)
{
ao_radio_abort = 1;
- ao_wakeup(&ao_radio_done);
+ ao_wakeup(&ao_radio_wake);
}
#define ao_radio_rdf_value 0x55
-static const uint16_t rdf_setup[] = {
+/*
+ * RDF deviation is 5kHz
+ *
+ * fdev = fosc >> 24 * (256 + dev_m) << dev_e
+ *
+ * 32e6Hz / (2 ** 24) * (256 + 71) * (2 ** 3) = 4989
+ */
+
+#define RDF_DEV_E 3
+#define RDF_DEV_M 71
+#define RDF_PACKET_LEN 50
+
+/*
+ * For our RDF beacon, set the symbol rate to 2kBaud (for a 1kHz tone)
+ *
+ * (2**20 - DATARATE_M) * 2 ** DATARATE_E
+ * Rdata = -------------------------------------- * fosc
+ * 2 ** 39
+ *
+ * DATARATE_M = 511705
+ * DATARATE_E = 6
+ *
+ * To make the tone last for 200ms, we need 2000 * .2 = 400 bits or 50 bytes
+ */
+#define RDF_DRATE_E 5
+#define RDF_DRATE_M 25166
+#define RDF_PACKET_LEN 50
+
+static const uint16_t rdf_setup[] = {
+ CC1120_DEVIATION_M, RDF_DEV_M,
+ CC1120_MODCFG_DEV_E, ((CC1120_MODCFG_DEV_E_MODEM_MODE_NORMAL << CC1120_MODCFG_DEV_E_MODEM_MODE) |
+ (CC1120_MODCFG_DEV_E_MOD_FORMAT_2_GFSK << CC1120_MODCFG_DEV_E_MOD_FORMAT) |
+ (RDF_DEV_E << CC1120_MODCFG_DEV_E_DEV_E)),
+ CC1120_DRATE2, ((RDF_DRATE_E << CC1120_DRATE2_DATARATE_E) |
+ (((RDF_DRATE_M >> 16) & CC1120_DRATE2_DATARATE_M_19_16_MASK) << CC1120_DRATE2_DATARATE_M_19_16)),
+ CC1120_DRATE1, ((RDF_DRATE_M >> 8) & 0xff),
+ CC1120_DRATE0, ((RDF_DRATE_M >> 0) & 0xff),
+ CC1120_PKT_CFG2, ((CC1120_PKT_CFG2_CCA_MODE_ALWAYS_CLEAR << CC1120_PKT_CFG2_CCA_MODE) |
+ (CC1120_PKT_CFG2_PKT_FORMAT_NORMAL << CC1120_PKT_CFG2_PKT_FORMAT)),
+ CC1120_PKT_CFG1, ((0 << CC1120_PKT_CFG1_WHITE_DATA) |
+ (CC1120_PKT_CFG1_ADDR_CHECK_CFG_NONE << CC1120_PKT_CFG1_ADDR_CHECK_CFG) |
+ (CC1120_PKT_CFG1_CRC_CFG_DISABLED << CC1120_PKT_CFG1_CRC_CFG) |
+ (0 << CC1120_PKT_CFG1_APPEND_STATUS)),
+ CC1120_PKT_CFG0, ((0 << CC1120_PKT_CFG0_RESERVED7) |
+ (CC1120_PKT_CFG0_LENGTH_CONFIG_FIXED << CC1120_PKT_CFG0_LENGTH_CONFIG) |
+ (0 << CC1120_PKT_CFG0_PKG_BIT_LEN) |
+ (0 << CC1120_PKT_CFG0_UART_MODE_EN) |
+ (0 << CC1120_PKT_CFG0_UART_SWAP_EN)),
};
+static uint8_t
+ao_radio_marc_status(void)
+{
+ return ao_radio_reg_read(CC1120_MARC_STATUS1);
+}
+
+static uint8_t
+ao_radio_tx_done(void)
+{
+ return ao_radio_marc_status() == CC1120_MARC_STATUS1_TX_FINISHED;
+}
+
+static uint8_t
+ao_radio_rx_done(void)
+{
+ return ao_radio_marc_status() == CC1120_MARC_STATUS1_RX_FINISHED;
+}
+
+static void
+ao_radio_start_tx(void)
+{
+ ao_radio_reg_write(CC1120_IOCFG2, CC1120_IOCFG_GPIO_CFG_RX0TX1_CFG);
+ ao_exti_enable(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN);
+ ao_radio_strobe(CC1120_STX);
+}
+
void
ao_radio_rdf(uint8_t len)
{
int i;
- ao_radio_abort = 0;
ao_radio_get(len);
- ao_radio_done = 0;
+ ao_radio_wake = 0;
for (i = 0; i < sizeof (rdf_setup) / sizeof (rdf_setup[0]); i += 2)
ao_radio_reg_write(rdf_setup[i], rdf_setup[i+1]);
+
ao_radio_fifo_write_fixed(ao_radio_rdf_value, len);
- ao_radio_reg_write(CC1120_IOCFG2, CC1120_IOCFG_GPIO_CFG_RX0TX1_CFG);
- ao_exti_enable(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN);
- ao_radio_strobe(CC1120_STX);
+
+ ao_radio_start_tx();
+
cli();
- while (!ao_radio_done)
- ao_sleep(&ao_radio_done);
+ while (!ao_radio_wake && !ao_radio_abort)
+ ao_sleep(&ao_radio_wake);
+
sei();
+ if (!ao_radio_tx_done())
+ ao_radio_idle();
ao_radio_set_packet();
ao_radio_put();
}
void
ao_radio_rdf_abort(void)
{
+ ao_radio_abort = 1;
+ ao_wakeup(&ao_radio_wake);
}
static void
#endif
ao_radio_get(0xff);
ao_radio_strobe(CC1120_STX);
+#if CC1120_TRACE
+ { int t;
+ for (t = 0; t < 10; t++) {
+ printf ("status: %02x\n", ao_radio_status());
+ ao_delay(AO_MS_TO_TICKS(100));
+ }
+ }
+#endif
radio_on = 1;
}
if (mode == 3) {
void
ao_radio_send(void *d, uint8_t size)
{
+ uint8_t marc_status;
+ static uint8_t prepare[128];
+ uint8_t prepare_len;
+ static uint8_t encode[256];
+ uint8_t encode_len;
+ static uint8_t interleave[256];
+ uint8_t interleave_len;
+
+ ao_fec_dump_bytes(d, size, "Input");
+
+#if 1
+ prepare_len = ao_fec_prepare(d, size, prepare);
+ ao_fec_dump_bytes(prepare, prepare_len, "Prepare");
+
+ ao_fec_whiten(prepare, prepare_len, prepare);
+ ao_fec_dump_bytes(prepare, prepare_len, "Whiten");
+
+ encode_len = ao_fec_encode(prepare, prepare_len, encode);
+ ao_fec_dump_bytes(encode, encode_len, "Encode");
+
+ interleave_len = ao_fec_interleave(encode, encode_len, interleave);
+ ao_fec_dump_bytes(interleave, interleave_len, "Interleave");
+ ao_radio_get(interleave_len);
+ ao_radio_fifo_write(interleave, interleave_len);
+#else
ao_radio_get(size);
- ao_radio_done = 0;
ao_radio_fifo_write(d, size);
- ao_radio_reg_write(CC1120_IOCFG2, CC1120_IOCFG_GPIO_CFG_RX0TX1_CFG);
- ao_exti_enable(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN);
- ao_radio_strobe(CC1120_STX);
+#endif
+
+ ao_radio_wake = 0;
+
+ ao_radio_start_tx();
+
cli();
- while (!ao_radio_done)
- ao_sleep(&ao_radio_done);
+ while (!ao_radio_wake && !ao_radio_abort)
+ ao_sleep(&ao_radio_wake);
sei();
+ if (!ao_radio_tx_done())
+ ao_radio_idle();
ao_radio_put();
}
uint8_t
ao_radio_recv(__xdata void *d, uint8_t size)
{
+ uint8_t marc_status = CC1120_MARC_STATUS1_NO_FAILURE;
+
/* configure interrupt pin */
ao_radio_get(size);
- ao_radio_done = 0;
- ao_radio_reg_write(CC1120_IOCFG2, CC1120_IOCFG_GPIO_CFG_RXFIFO_THR_PKT);
+ ao_radio_wake = 0;
ao_exti_enable(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN);
ao_radio_strobe(CC1120_SRX);
cli();
- while (!ao_radio_done && !ao_radio_abort)
- ao_sleep(&ao_radio_done);
+ for (;;) {
+ if (ao_radio_abort)
+
+ break;
+ if (ao_radio_wake) {
+ marc_status = ao_radio_marc_status();
+ if (marc_status != CC1120_MARC_STATUS1_NO_FAILURE)
+ break;
+ ao_radio_wake = 0;
+ }
+ ao_sleep(&ao_radio_wake);
+ }
sei();
- if (ao_radio_done)
+ if (marc_status != CC1120_MARC_STATUS1_RX_FINISHED)
ao_radio_fifo_read(d, size);
ao_radio_put();
- return 0;
+ return marc_status == CC1120_MARC_STATUS1_RX_FINISHED;
}
+/*
+ * Packet deviation is 20.5kHz
+ *
+ * fdev = fosc >> 24 * (256 + dev_m) << dev_e
+ *
+ * 32e6Hz / (2 ** 24) * (256 + 80) * (2 ** 5) = 20508Hz
+ */
+
+#define PACKET_DEV_E 5
+#define PACKET_DEV_M 80
+
+/*
+ * For our packet data, set the symbol rate to 38360 Baud
+ *
+ * (2**20 + DATARATE_M) * 2 ** DATARATE_E
+ * Rdata = -------------------------------------- * fosc
+ * 2 ** 39
+ *
+ *
+ * DATARATE_M = 239914
+ * DATARATE_E = 9
+ */
+#define PACKET_DRATE_E 9
+#define PACKET_DRATE_M 239914
+
static const uint16_t packet_setup[] = {
+ CC1120_DEVIATION_M, PACKET_DEV_M,
+ CC1120_MODCFG_DEV_E, ((CC1120_MODCFG_DEV_E_MODEM_MODE_NORMAL << CC1120_MODCFG_DEV_E_MODEM_MODE) |
+ (CC1120_MODCFG_DEV_E_MOD_FORMAT_2_GFSK << CC1120_MODCFG_DEV_E_MOD_FORMAT) |
+ (PACKET_DEV_E << CC1120_MODCFG_DEV_E_DEV_E)),
+ CC1120_DRATE2, ((PACKET_DRATE_E << CC1120_DRATE2_DATARATE_E) |
+ (((PACKET_DRATE_M >> 16) & CC1120_DRATE2_DATARATE_M_19_16_MASK) << CC1120_DRATE2_DATARATE_M_19_16)),
+ CC1120_DRATE1, ((PACKET_DRATE_M >> 8) & 0xff),
+ CC1120_DRATE0, ((PACKET_DRATE_M >> 0) & 0xff),
+ CC1120_PKT_CFG2, ((CC1120_PKT_CFG2_CCA_MODE_ALWAYS_CLEAR << CC1120_PKT_CFG2_CCA_MODE) |
+ (CC1120_PKT_CFG2_PKT_FORMAT_NORMAL << CC1120_PKT_CFG2_PKT_FORMAT)),
+ CC1120_PKT_CFG1, ((0 << CC1120_PKT_CFG1_WHITE_DATA) |
+ (CC1120_PKT_CFG1_ADDR_CHECK_CFG_NONE << CC1120_PKT_CFG1_ADDR_CHECK_CFG) |
+ (CC1120_PKT_CFG1_CRC_CFG_DISABLED << CC1120_PKT_CFG1_CRC_CFG) |
+ (1 << CC1120_PKT_CFG1_APPEND_STATUS)),
+ CC1120_PKT_CFG0, ((0 << CC1120_PKT_CFG0_RESERVED7) |
+ (CC1120_PKT_CFG0_LENGTH_CONFIG_FIXED << CC1120_PKT_CFG0_LENGTH_CONFIG) |
+ (0 << CC1120_PKT_CFG0_PKG_BIT_LEN) |
+ (0 << CC1120_PKT_CFG0_UART_MODE_EN) |
+ (0 << CC1120_PKT_CFG0_UART_SWAP_EN)),
};
void
if ((state >> CC1120_STATUS_STATE) == CC1120_STATUS_STATE_IDLE)
break;
}
+ ao_radio_strobe(CC1120_SFTX);
+ ao_radio_strobe(CC1120_SFRX);
}
static const uint16_t radio_setup[] = {
ao_radio_isr(void)
{
ao_exti_disable(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN);
- ao_radio_done = 1;
- ao_wakeup(&ao_radio_done);
+ ao_radio_wake = 1;
+ ao_wakeup(&ao_radio_wake);
}
static void
{
int i;
+ ao_radio_strobe(CC1120_SRES);
+
for (i = 0; i < sizeof (radio_setup) / sizeof (radio_setup[0]); i += 2)
ao_radio_reg_write(radio_setup[i], radio_setup[i+1]);
- /* Disable GPIO2 pin (radio_int) */
- ao_radio_reg_write(CC1120_IOCFG2, CC1120_IOCFG_GPIO_CFG_HIGHZ);
+ ao_radio_set_packet();
- /* Enable the EXTI interrupt for the appropriate pin */
- ao_enable_port(AO_CC1120_INT_PORT);
- ao_exti_setup(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN, AO_EXTI_MODE_RISING, ao_radio_isr);
+ ao_config_get();
- ao_radio_set_packet();
ao_radio_configured = 1;
}
ao_mutex_get(&ao_radio_mutex);
if (!ao_radio_configured)
ao_radio_setup();
+ ao_radio_reg_write(CC1120_FREQ2, ao_config.radio_setting >> 16);
+ ao_radio_reg_write(CC1120_FREQ1, ao_config.radio_setting >> 8);
+ ao_radio_reg_write(CC1120_FREQ0, ao_config.radio_setting);
ao_radio_reg_write(CC1120_PKT_LEN, len);
}
printf ("Status: %02x\n", status);
printf ("CHIP_RDY: %d\n", (status >> CC1120_STATUS_CHIP_RDY) & 1);
printf ("STATE: %s\n", cc1120_state_name[(status >> CC1120_STATUS_STATE) & CC1120_STATUS_STATE_MASK]);
+ printf ("MARC: %02x\n", ao_radio_marc_status());
for (i = 0; i < AO_NUM_CC1120_REG; i++)
printf ("\t%02x %-20.20s\n", ao_radio_reg_read(ao_cc1120_reg[i].addr), ao_cc1120_reg[i].name);
ao_radio_put();
}
+
+static void ao_radio_beep(void) {
+ ao_radio_rdf(RDF_PACKET_LEN);
+}
+
+static void ao_radio_packet(void) {
+ static uint8_t packet[] = {
+#if 1
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+#else
+ 3, 1, 2, 3
+#endif
+ };
+
+ ao_radio_send(packet, sizeof (packet));
+}
+
#endif
static const struct ao_cmds ao_radio_cmds[] = {
{ ao_radio_test, "C <1 start, 0 stop, none both>\0Radio carrier test" },
#if CC1120_DEBUG
{ ao_radio_show, "R\0Show CC1120 status" },
+ { ao_radio_beep, "b\0Emit an RDF beacon" },
+ { ao_radio_packet, "p\0Send a test packet" },
#endif
{ 0, NULL }
};
void
ao_radio_init(void)
{
+ int i;
+
ao_radio_configured = 0;
ao_spi_init_cs (AO_CC1120_SPI_CS_PORT, (1 << AO_CC1120_SPI_CS_PIN));
+ AO_CC1120_SPI_CS_PORT.bsrr = ((uint32_t) (1 << AO_CC1120_SPI_CS_PIN));
+ for (i = 0; i < 10000; i++) {
+ if ((SPI_2_GPIO.idr & (1 << SPI_2_MISO)) == 0)
+ break;
+ }
+ AO_CC1120_SPI_CS_PORT.bsrr = (1 << AO_CC1120_SPI_CS_PIN);
+ if (i == 10000)
+ ao_panic(AO_PANIC_SELF_TEST);
+
+ /* Enable the EXTI interrupt for the appropriate pin */
+ ao_enable_port(AO_CC1120_INT_PORT);
+ ao_exti_setup(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN, AO_EXTI_MODE_FALLING, ao_radio_isr);
+
ao_cmd_register(&ao_radio_cmds[0]);
}
projects / fw / altos / blobdiff