altosui: Eliminate ao_cmd_filter hook

[fw/altos] / src / cc1111.h

diff --git a/src/cc1111.h b/src/cc1111.h
index 20ed052a1d5cf600dd1eabd7c6078b9542cc0781..a07490e52bc2ffa697cb2580e4506e1713735db0 100644 (file)
--- a/src/cc1111.h
+++ b/src/cc1111.h
@@ -565,14 +565,19 @@ sfr at 0xF5 P2SEL;
 #define P2SEL_PRI3P1_MASK              (1 << 6)
 #define P2SEL_PRI2P1_USART1            (0 << 5)
 #define P2SEL_PRI2P1_TIMER3            (1 << 5)
+#define P2SEL_PRI2P1_MASK              (1 << 5)
 #define P2SEL_PRI1P1_TIMER1            (0 << 4)
 #define P2SEL_PRI1P1_TIMER4            (1 << 4)
+#define P2SEL_PRI1P1_MASK              (1 << 4)
 #define P2SEL_PRI0P1_USART0            (0 << 3)
 #define P2SEL_PRI0P1_TIMER1            (1 << 3)
+#define P2SEL_PRI0P1_MASK              (1 << 3)
 #define P2SEL_SELP2_4_GPIO             (0 << 2)
 #define P2SEL_SELP2_4_PERIPHERAL       (1 << 2)
+#define P2SEL_SELP2_4_MASK             (1 << 2)
 #define P2SEL_SELP2_3_GPIO             (0 << 1)
 #define P2SEL_SELP2_3_PERIPHERAL       (1 << 1)
+#define P2SEL_SELP2_3_MASK             (1 << 1)
 #define P2SEL_SELP2_0_GPIO             (0 << 0)
 #define P2SEL_SELP2_0_PERIPHERAL       (1 << 0)
 #define P2SEL_SELP2_0_MASK             (1 << 0)
@@ -657,6 +662,14 @@ sfr at 0x8B P2IFG;
 
 #define P0IFG_USB_RESUME       (1 << 7)
 
+sfr at 0x8C PICTL;
+#define PICTL_P2IEN    (1 << 5)
+#define PICTL_P0IENH   (1 << 4)
+#define PICTL_P0IENL   (1 << 3)
+#define PICTL_P2ICON   (1 << 2)
+#define PICTL_P1ICON   (1 << 1)
+#define PICTL_P0ICON   (1 << 0)
+
 /* GPIO pins */
 sfr at 0x80 P0;
 
@@ -884,6 +897,26 @@ __xdata __at (0xDFF9) volatile uint8_t U1DBUFXADDR;
 sfr at 0xc2 U0BAUD;
 sfr at 0xfa U1BAUD;
 
+/* Flash controller */
+
+sfr at 0xAE FCTL;
+#define FCTL_BUSY              (1 << 7)
+#define FCTL_SWBSY             (1 << 6)
+#define FCTL_CONTRD_ENABLE     (1 << 4)
+#define FCTL_WRITE             (1 << 1)
+#define FCTL_ERASE             (1 << 0)
+
+/* Flash write data. Write two bytes here */
+sfr at 0xAF FWDATA;
+__xdata __at (0xDFAF) volatile uint8_t FWDATAXADDR;
+
+/* Flash write/erase address */
+sfr at 0xAD FADDRH;
+sfr at 0xAC FADDRL;
+
+/* Flash timing */
+sfr at 0xAB FWT;
+
 /* Radio */
 
 sfr at 0xD9 RFD;