[x_have_usbdevice_fs_h=yes],
[x_have_usbdevice_fs_h=no])
if test x${x_have_usbdevice_fs_h} = xyes; then
- FUSB_TECH=libusb1
+ FUSB_TECH=linux
else
- FUSB_TECH=libusb1
+ FUSB_TECH=generic
fi
;;
darwin*)
AM_CONDITIONAL(FUSB_TECH_darwin, test x$FUSB_TECH = xdarwin)
AM_CONDITIONAL(FUSB_TECH_win32, test x$FUSB_TECH = xwin32)
AM_CONDITIONAL(FUSB_TECH_generic, test x$FUSB_TECH = xgeneric)
- AM_CONDITIONAL(FUSB_TECH_libusb1, test x$FUSB_TECH = xlibusb1)
AM_CONDITIONAL(FUSB_TECH_linux, test x$FUSB_TECH = xlinux)
+ AM_CONDITIONAL(FUSB_TECH_libusb1, test x$FUSB_TECH = xlibusb1)
AM_CONDITIONAL(FUSB_TECH_ra_wb, test x$FUSB_TECH = xra_wb)
])
AC_DEFUN([USRP_LIBUSB], [
libusbok=yes
- PKG_CHECK_MODULES(USB, libusb-1.0, [], [
+ PKG_CHECK_MODULES(USB, libusb, [], [
AC_LANG_PUSH(C)
- AC_CHECK_HEADERS([libusb.h], [], [libusbok=no; AC_MSG_RESULT([USRP requires libusb1. usb.h not found. See http://libusb.sf.net])])
+ AC_CHECK_HEADERS([usb.h], [], [libusbok=no; AC_MSG_RESULT([USRP requires libusb. usb.h not found. See http://libusb.sf.net])])
save_LIBS="$LIBS"
case "$host_os" in
#include <boost/utility.hpp>
#include <usrp/usrp_subdev_spec.h>
+#if 1
+struct usb_dev_handle;
+struct usb_device;
+typedef struct usb_dev_handle libusb_device_handle;
+typedef struct usb_device libusb_device;
+#else
struct libusb_device_handle;
+#endif
+
class fusb_devhandle;
class fusb_ephandle;
void shutdown_daughterboards();
protected:
- struct libusb_device_handle *d_udh;
+ libusb_device_handle *d_udh;
struct libusb_context *d_ctx;
int d_usb_data_rate; // bytes/sec
int d_bytes_per_poll; // how often to poll for overruns
usrp_basic (int which_board,
- struct libusb_device_handle *open_interface (struct libusb_device *dev),
+ libusb_device_handle *open_interface (libusb_device *dev),
const std::string fpga_filename = "",
const std::string firmware_filename = "");
enum usrp_load_status_t { ULS_ERROR = 0, ULS_OK, ULS_ALREADY_LOADED };
+#if 1
+struct usb_dev_handle;
+struct usb_device;
+typedef struct usb_dev_handle libusb_device_handle;
+typedef struct usb_device libusb_device;
+#else
struct libusb_device_handle;
struct libusb_device;
+#endif
+
struct libusb_context;
/*!
*/
libusb_context* usrp_one_time_init (bool new_context);
+void usrp_one_time_init ();
+
/*
* force a rescan of the buses and devices
*/
* configured USRP (firmware loaded)
* unconfigured Cypress FX2 (only if fx2_ok_p is true)
*/
-struct libusb_device *usrp_find_device (int nth, bool fx2_ok_p = false, libusb_context *ctx = NULL);
+libusb_device *usrp_find_device (int nth, bool fx2_ok_p = false, libusb_context *ctx = NULL);
-bool usrp_usrp_p (struct libusb_device *q); //< is this a USRP
-bool usrp_usrp0_p (struct libusb_device *q); //< is this a USRP Rev 0
-bool usrp_usrp1_p (struct libusb_device *q); //< is this a USRP Rev 1
-bool usrp_usrp2_p (struct libusb_device *q); //< is this a USRP Rev 2
-int usrp_hw_rev (struct libusb_device *q); //< return h/w rev code
+bool usrp_usrp_p (libusb_device *q); //< is this a USRP
+bool usrp_usrp0_p (libusb_device *q); //< is this a USRP Rev 0
+bool usrp_usrp1_p (libusb_device *q); //< is this a USRP Rev 1
+bool usrp_usrp2_p (libusb_device *q); //< is this a USRP Rev 2
+int usrp_hw_rev (libusb_device *q); //< return h/w rev code
-bool usrp_fx2_p (struct libusb_device *q); //< is this an unconfigured Cypress FX2
+bool usrp_fx2_p (libusb_device *q); //< is this an unconfigured Cypress FX2
-bool usrp_unconfigured_usrp_p (struct libusb_device *q); //< some kind of unconfigured USRP
-bool usrp_configured_usrp_p (struct libusb_device *q); //< some kind of configured USRP
+bool usrp_unconfigured_usrp_p (libusb_device *q); //< some kind of unconfigured USRP
+bool usrp_configured_usrp_p (libusb_device *q); //< some kind of configured USRP
/*!
* \brief given a libusb_device return an instance of the appropriate libusb_device_handle
* If interface can't be opened, or is already claimed by some other
* process, 0 is returned.
*/
-struct libusb_device_handle *usrp_open_cmd_interface (struct libusb_device *dev);
-struct libusb_device_handle *usrp_open_rx_interface (struct libusb_device *dev);
-struct libusb_device_handle *usrp_open_tx_interface (struct libusb_device *dev);
+libusb_device_handle *usrp_open_cmd_interface (libusb_device *dev);
+libusb_device_handle *usrp_open_rx_interface (libusb_device *dev);
+libusb_device_handle *usrp_open_tx_interface (libusb_device *dev);
/*!
* \brief close interface.
*/
-bool usrp_close_interface (struct libusb_device_handle *udh);
+bool usrp_close_interface (libusb_device_handle *udh);
/*!
* \brief load intel hex format file into USRP/Cypress FX2 (8051).
*/
usrp_load_status_t
-usrp_load_firmware (struct libusb_device_handle *udh, const char *filename, bool force);
+usrp_load_firmware (libusb_device_handle *udh, const char *filename, bool force);
/*!
* \brief load intel hex format file into USRP FX2 (8051).
* then rescans the busses and devices.
*/
usrp_load_status_t
-usrp_load_firmware_nth (int nth, const char *filename, bool force, libusb_context *ctx);
+usrp_load_firmware_nth (int nth, const char *filename, bool force, libusb_context *ctx = NULL);
/*!
* \brief load fpga configuration bitstream
*/
usrp_load_status_t
-usrp_load_fpga (struct libusb_device_handle *udh, const char *filename, bool force);
+usrp_load_fpga (libusb_device_handle *udh, const char *filename, bool force);
/*!
* \brief load the regular firmware and fpga bitstream in the Nth USRP.
* \brief copy the given \p hash into the USRP hash slot \p which.
* The usrp implements two hash slots, 0 and 1.
*/
-bool usrp_set_hash (struct libusb_device_handle *udh, int which,
+bool usrp_set_hash (libusb_device_handle *udh, int which,
const unsigned char hash[USRP_HASH_SIZE]);
/*!
* \brief retrieve the \p hash from the USRP hash slot \p which.
* The usrp implements two hash slots, 0 and 1.
*/
-bool usrp_get_hash (struct libusb_device_handle *udh, int which,
+bool usrp_get_hash (libusb_device_handle *udh, int which,
unsigned char hash[USRP_HASH_SIZE]);
-bool usrp_write_fpga_reg (struct libusb_device_handle *udh, int reg, int value);
-bool usrp_read_fpga_reg (struct libusb_device_handle *udh, int reg, int *value);
-bool usrp_set_fpga_reset (struct libusb_device_handle *udh, bool on);
-bool usrp_set_fpga_tx_enable (struct libusb_device_handle *udh, bool on);
-bool usrp_set_fpga_rx_enable (struct libusb_device_handle *udh, bool on);
-bool usrp_set_fpga_tx_reset (struct libusb_device_handle *udh, bool on);
-bool usrp_set_fpga_rx_reset (struct libusb_device_handle *udh, bool on);
-bool usrp_set_led (struct libusb_device_handle *udh, int which, bool on);
+bool usrp_write_fpga_reg (libusb_device_handle *udh, int reg, int value);
+bool usrp_read_fpga_reg (libusb_device_handle *udh, int reg, int *value);
+bool usrp_set_fpga_reset (libusb_device_handle *udh, bool on);
+bool usrp_set_fpga_tx_enable (libusb_device_handle *udh, bool on);
+bool usrp_set_fpga_rx_enable (libusb_device_handle *udh, bool on);
+bool usrp_set_fpga_tx_reset (libusb_device_handle *udh, bool on);
+bool usrp_set_fpga_rx_reset (libusb_device_handle *udh, bool on);
+bool usrp_set_led (libusb_device_handle *udh, int which, bool on);
-bool usrp_check_rx_overrun (struct libusb_device_handle *udh, bool *overrun_p);
-bool usrp_check_tx_underrun (struct libusb_device_handle *udh, bool *underrun_p);
+bool usrp_check_rx_overrun (libusb_device_handle *udh, bool *overrun_p);
+bool usrp_check_tx_underrun (libusb_device_handle *udh, bool *underrun_p);
// i2c_read and i2c_write are limited to a maximum len of 64 bytes.
-bool usrp_i2c_write (struct libusb_device_handle *udh, int i2c_addr,
+bool usrp_i2c_write (libusb_device_handle *udh, int i2c_addr,
const void *buf, int len);
-bool usrp_i2c_read (struct libusb_device_handle *udh, int i2c_addr,
+bool usrp_i2c_read (libusb_device_handle *udh, int i2c_addr,
void *buf, int len);
// spi_read and spi_write are limited to a maximum of 64 bytes
// See usrp_spi_defs.h for more info
-bool usrp_spi_write (struct libusb_device_handle *udh,
+bool usrp_spi_write (libusb_device_handle *udh,
int optional_header, int enables, int format,
const void *buf, int len);
-bool usrp_spi_read (struct libusb_device_handle *udh,
+bool usrp_spi_read (libusb_device_handle *udh,
int optional_header, int enables, int format,
void *buf, int len);
-bool usrp_9862_write (struct libusb_device_handle *udh,
+bool usrp_9862_write (libusb_device_handle *udh,
int which_codec, // [0, 1]
int regno, // [0, 63]
int value); // [0, 255]
-bool usrp_9862_read (struct libusb_device_handle *udh,
+bool usrp_9862_read (libusb_device_handle *udh,
int which_codec, // [0, 1]
int regno, // [0, 63]
unsigned char *value); // [0, 255]
* \p buf contains alternating register_number, register_value pairs.
* \p len must be even and is the length of buf in bytes.
*/
-bool usrp_9862_write_many (struct libusb_device_handle *udh, int which_codec,
+bool usrp_9862_write_many (libusb_device_handle *udh, int which_codec,
const unsigned char *buf, int len);
/*!
* \brief write specified regs to all 9862's in the system
*/
-bool usrp_9862_write_many_all (struct libusb_device_handle *udh,
+bool usrp_9862_write_many_all (libusb_device_handle *udh,
const unsigned char *buf, int len);
// Write 24LC024 / 24LC025 EEPROM on motherboard or daughterboard.
// Which EEPROM is determined by i2c_addr. See i2c_addr.h
-bool usrp_eeprom_write (struct libusb_device_handle *udh, int i2c_addr,
+bool usrp_eeprom_write (libusb_device_handle *udh, int i2c_addr,
int eeprom_offset, const void *buf, int len);
// Read 24LC024 / 24LC025 EEPROM on motherboard or daughterboard.
// Which EEPROM is determined by i2c_addr. See i2c_addr.h
-bool usrp_eeprom_read (struct libusb_device_handle *udh, int i2c_addr,
+bool usrp_eeprom_read (libusb_device_handle *udh, int i2c_addr,
int eeprom_offset, void *buf, int len);
* binary values. Although dacs 0, 1 and 2 are 8-bit and dac 3 is 12-bit,
* the interface is in terms of 12-bit values [0,4095]
*/
-bool usrp_write_aux_dac (struct libusb_device_handle *uhd, int slot,
+bool usrp_write_aux_dac (libusb_device_handle *uhd, int slot,
int which_dac, int value);
/*!
* \p which_adc: [0,1] which of the two adcs to read
* \p *value: return value, 12-bit straight binary.
*/
-bool usrp_read_aux_adc (struct libusb_device_handle *udh, int slot,
+bool usrp_read_aux_adc (libusb_device_handle *udh, int slot,
int which_adc, int *value);
* \brief Read and return parsed daughterboard eeprom
*/
usrp_dbeeprom_status_t
-usrp_read_dboard_eeprom (struct libusb_device_handle *udh,
+usrp_read_dboard_eeprom (libusb_device_handle *udh,
int slot_id, usrp_dboard_eeprom *eeprom);
/*!
* \brief write ADC/DAC offset calibration constants to d'board eeprom
*/
-bool usrp_write_dboard_offsets (struct libusb_device_handle *udh, int slot_id,
+bool usrp_write_dboard_offsets (libusb_device_handle *udh, int slot_id,
short offset0, short offset1);
/*!
* Note that this only works on a configured usrp.
* \returns non-zero length string iff successful.
*/
-std::string usrp_serial_number(struct libusb_device_handle *udh);
+std::string usrp_serial_number(libusb_device_handle *udh);
#endif /* _USRP_PRIMS_H_ */
linux_CODE = \
fusb_linux.cc \
- fusb_sysconfig_linux.cc
+ fusb_sysconfig_linux.cc \
+ usrp_prims_libusb.cc \
+ usrp_basic_libusb.cc
ra_wb_CODE = \
fusb_ra_wb.cc \
libusb1_CODE = \
fusb_libusb1.cc \
- fusb_sysconfig_libusb1.cc
+ fusb_sysconfig_libusb1.cc \
+ usrp_prims_libusb1.cc \
+ usrp_basic_libusb1.cc
#
# include each <foo>_CODE entry here...
libusrp_la_common_SOURCES = \
fusb.cc \
md5.c \
- usrp_basic.cc \
+ usrp_basic_common.cc \
usrp_config.cc \
usrp_dbid.cc \
usrp_local_sighandler.cc \
- usrp_prims.cc \
+ usrp_prims_common.cc \
usrp_standard.cc \
db_boards.cc \
db_base.cc \
db_basic.cc \
db_tv_rx.cc \
- db_tv_rx_mimo.cc \
+ db_tv_rx_mimo.cc \
db_flexrf.cc \
db_flexrf_mimo.cc \
db_dbs_rx.cc \
#define _FUSB_H_
+#if 1
+struct usb_dev_handle;
+typedef struct usb_dev_handle libusb_device_handle;
+#else
struct libusb_device_handle;
+#endif
+
struct libusb_context;
class fusb_ephandle;
static fusb_devhandle *make_devhandle (libusb_device_handle *udh,
libusb_context *ctx);
+ static fusb_devhandle *make_devhandle (libusb_device_handle *udh);
+
/*!
* \brief Returns max block size in bytes (hard limit).
*/
return new fusb_devhandle_linux (udh);
}
+fusb_devhandle *
+fusb_sysconfig::make_devhandle (usb_dev_handle *udh, libusb_context *ctx)
+{
+ return new fusb_devhandle_linux (udh);
+}
+
int fusb_sysconfig::max_block_size ()
{
return MAX_BLOCK_SIZE;
+++ /dev/null
-/* -*- c++ -*- */
-/*
- * Copyright 2003,2004,2008,2009 Free Software Foundation, Inc.
- *
- * This file is part of GNU Radio
- *
- * GNU Radio is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 3, or (at your option)
- * any later version.
- *
- * GNU Radio is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with GNU Radio; see the file COPYING. If not, write to
- * the Free Software Foundation, Inc., 51 Franklin Street,
- * Boston, MA 02110-1301, USA.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <usrp/usrp_basic.h>
-#include "usrp/usrp_prims.h"
-#include "usrp_interfaces.h"
-#include "fpga_regs_common.h"
-#include "fpga_regs_standard.h"
-#include "fusb.h"
-#include "db_boards.h"
-#include <libusb-1.0/libusb.h>
-#include <stdexcept>
-#include <assert.h>
-#include <math.h>
-#include <ad9862.h>
-#include <string.h>
-#include <cstdio>
-
-using namespace ad9862;
-
-#define NELEM(x) (sizeof (x) / sizeof (x[0]))
-
-// These set the buffer size used for each end point using the fast
-// usb interface. The kernel ends up locking down this much memory.
-
-static const int FUSB_BUFFER_SIZE = fusb_sysconfig::default_buffer_size();
-static const int FUSB_BLOCK_SIZE = fusb_sysconfig::max_block_size();
-static const int FUSB_NBLOCKS = FUSB_BUFFER_SIZE / FUSB_BLOCK_SIZE;
-
-
-static const double POLLING_INTERVAL = 0.1; // seconds
-
-////////////////////////////////////////////////////////////////
-
-static struct libusb_device_handle *
-open_rx_interface (struct libusb_device *dev)
-{
- struct libusb_device_handle *udh = usrp_open_rx_interface (dev);
- if (udh == 0){
- fprintf (stderr, "usrp_basic_rx: can't open rx interface\n");
- }
- return udh;
-}
-
-static struct libusb_device_handle *
-open_tx_interface (struct libusb_device *dev)
-{
- struct libusb_device_handle *udh = usrp_open_tx_interface (dev);
- if (udh == 0){
- fprintf (stderr, "usrp_basic_tx: can't open tx interface\n");
- }
- return udh;
-}
-
-
-//////////////////////////////////////////////////////////////////
-//
-// usrp_basic
-//
-////////////////////////////////////////////////////////////////
-
-
-// Given:
-// CLKIN = 64 MHz
-// CLKSEL pin = high
-//
-// These settings give us:
-// CLKOUT1 = CLKIN = 64 MHz
-// CLKOUT2 = CLKIN = 64 MHz
-// ADC is clocked at 64 MHz
-// DAC is clocked at 128 MHz
-
-static unsigned char common_regs[] = {
- REG_GENERAL, 0,
- REG_DLL, (DLL_DISABLE_INTERNAL_XTAL_OSC
- | DLL_MULT_2X
- | DLL_FAST),
- REG_CLKOUT, CLKOUT2_EQ_DLL_OVER_2,
- REG_AUX_ADC_CLK, AUX_ADC_CLK_CLK_OVER_4
-};
-
-
-usrp_basic::usrp_basic (int which_board,
- struct libusb_device_handle *
- open_interface (struct libusb_device *dev),
- const std::string fpga_filename,
- const std::string firmware_filename)
- : d_udh (0), d_ctx (0),
- d_usb_data_rate (16000000), // SWAG, see below
- d_bytes_per_poll ((int) (POLLING_INTERVAL * d_usb_data_rate)),
- d_verbose (false), d_fpga_master_clock_freq(64000000), d_db(2)
-{
- /*
- * SWAG: Scientific Wild Ass Guess.
- *
- * d_usb_data_rate is used only to determine how often to poll for over- and under-runs.
- * We defualt it to 1/2 of our best case. Classes derived from usrp_basic (e.g.,
- * usrp_standard_tx and usrp_standard_rx) call set_usb_data_rate() to tell us the
- * actual rate. This doesn't change our throughput, that's determined by the signal
- * processing code in the FPGA (which we know nothing about), and the system limits
- * determined by libusb, fusb_*, and the underlying drivers.
- */
- memset (d_fpga_shadows, 0, sizeof (d_fpga_shadows));
-
- d_ctx = usrp_one_time_init(true);
-
- if (!usrp_load_standard_bits (which_board, false, fpga_filename, firmware_filename, d_ctx))
- throw std::runtime_error ("usrp_basic/usrp_load_standard_bits");
-
- struct libusb_device *dev = usrp_find_device (which_board, false, d_ctx);
- if (dev == 0){
- fprintf (stderr, "usrp_basic: can't find usrp[%d]\n", which_board);
- throw std::runtime_error ("usrp_basic/usrp_find_device");
- }
-
- if (!(usrp_usrp_p(dev) && usrp_hw_rev(dev) >= 1)){
- fprintf (stderr, "usrp_basic: sorry, this code only works with USRP revs >= 1\n");
- throw std::runtime_error ("usrp_basic/bad_rev");
- }
-
- if ((d_udh = open_interface (dev)) == 0)
- throw std::runtime_error ("usrp_basic/open_interface");
-
- // initialize registers that are common to rx and tx
-
- if (!usrp_9862_write_many_all (d_udh, common_regs, sizeof (common_regs))){
- fprintf (stderr, "usrp_basic: failed to init common AD9862 regs\n");
- throw std::runtime_error ("usrp_basic/init_9862");
- }
-
- _write_fpga_reg (FR_MODE, 0); // ensure we're in normal mode
- _write_fpga_reg (FR_DEBUG_EN, 0); // disable debug outputs
-
-}
-
-void
-usrp_basic::shutdown_daughterboards()
-{
- // nuke d'boards before we close down USB in ~usrp_basic
- // shutdown() will do any board shutdown while the USRP can still
- // be talked to
- for(size_t i = 0; i < d_db.size(); i++)
- for(size_t j = 0; j < d_db[i].size(); j++)
- d_db[i][j]->shutdown();
-}
-
-usrp_basic::~usrp_basic ()
-{
- // shutdown_daughterboards(); // call from ~usrp_basic_{tx,rx}
-
- d_db.resize(0); // forget db shared ptrs
-
- if (d_udh)
- libusb_close (d_udh);
-
- // Each object should be running in it's own context. If running in default
- // (NULL) context then something went wrong.
-
- assert (d_ctx != NULL);
- libusb_exit (d_ctx);
-}
-
-void
-usrp_basic::init_db(usrp_basic_sptr u)
-{
- if (u.get() != this)
- throw std::invalid_argument("u is not this");
-
- d_db[0] = instantiate_dbs(d_dbid[0], u, 0);
- d_db[1] = instantiate_dbs(d_dbid[1], u, 1);
-}
-
-std::vector<db_base_sptr>
-usrp_basic::db(int which_side)
-{
- which_side &= 0x1; // clamp it to avoid any reporting any errors
- return d_db[which_side];
-}
-
-bool
-usrp_basic::is_valid(const usrp_subdev_spec &ss)
-{
- if (ss.side < 0 || ss.side > 1)
- return false;
-
- if (ss.subdev < 0 || ss.subdev >= d_db[ss.side].size())
- return false;
-
- return true;
-}
-
-db_base_sptr
-usrp_basic::selected_subdev(const usrp_subdev_spec &ss)
-{
- if (!is_valid(ss))
- throw std::invalid_argument("invalid subdev_spec");
-
- return d_db[ss.side][ss.subdev];
-}
-
-bool
-usrp_basic::start ()
-{
- return true; // nop
-}
-
-bool
-usrp_basic::stop ()
-{
- return true; // nop
-}
-
-void
-usrp_basic::set_usb_data_rate (int usb_data_rate)
-{
- d_usb_data_rate = usb_data_rate;
- d_bytes_per_poll = (int) (usb_data_rate * POLLING_INTERVAL);
-}
-
-bool
-usrp_basic::_write_aux_dac (int slot, int which_dac, int value)
-{
- return usrp_write_aux_dac (d_udh, slot, which_dac, value);
-}
-
-bool
-usrp_basic::_read_aux_adc (int slot, int which_adc, int *value)
-{
- return usrp_read_aux_adc (d_udh, slot, which_adc, value);
-}
-
-int
-usrp_basic::_read_aux_adc (int slot, int which_adc)
-{
- int value;
- if (!_read_aux_adc (slot, which_adc, &value))
- return READ_FAILED;
-
- return value;
-}
-
-bool
-usrp_basic::write_eeprom (int i2c_addr, int eeprom_offset, const std::string buf)
-{
- return usrp_eeprom_write (d_udh, i2c_addr, eeprom_offset, buf.data (), buf.size ());
-}
-
-std::string
-usrp_basic::read_eeprom (int i2c_addr, int eeprom_offset, int len)
-{
- if (len <= 0)
- return "";
-
- char buf[len];
-
- if (!usrp_eeprom_read (d_udh, i2c_addr, eeprom_offset, buf, len))
- return "";
-
- return std::string (buf, len);
-}
-
-bool
-usrp_basic::write_i2c (int i2c_addr, const std::string buf)
-{
- return usrp_i2c_write (d_udh, i2c_addr, buf.data (), buf.size ());
-}
-
-std::string
-usrp_basic::read_i2c (int i2c_addr, int len)
-{
- if (len <= 0)
- return "";
-
- char buf[len];
-
- if (!usrp_i2c_read (d_udh, i2c_addr, buf, len))
- return "";
-
- return std::string (buf, len);
-}
-
-std::string
-usrp_basic::serial_number()
-{
- return usrp_serial_number(d_udh);
-}
-
-// ----------------------------------------------------------------
-
-bool
-usrp_basic::set_adc_offset (int which_adc, int offset)
-{
- if (which_adc < 0 || which_adc > 3)
- return false;
-
- return _write_fpga_reg (FR_ADC_OFFSET_0 + which_adc, offset);
-}
-
-bool
-usrp_basic::set_dac_offset (int which_dac, int offset, int offset_pin)
-{
- if (which_dac < 0 || which_dac > 3)
- return false;
-
- int which_codec = which_dac >> 1;
- int tx_a = (which_dac & 0x1) == 0;
- int lo = ((offset & 0x3) << 6) | (offset_pin & 0x1);
- int hi = (offset >> 2);
- bool ok;
-
- if (tx_a){
- ok = _write_9862 (which_codec, REG_TX_A_OFFSET_LO, lo);
- ok &= _write_9862 (which_codec, REG_TX_A_OFFSET_HI, hi);
- }
- else {
- ok = _write_9862 (which_codec, REG_TX_B_OFFSET_LO, lo);
- ok &= _write_9862 (which_codec, REG_TX_B_OFFSET_HI, hi);
- }
- return ok;
-}
-
-bool
-usrp_basic::set_adc_buffer_bypass (int which_adc, bool bypass)
-{
- if (which_adc < 0 || which_adc > 3)
- return false;
-
- int codec = which_adc >> 1;
- int reg = (which_adc & 1) == 0 ? REG_RX_A : REG_RX_B;
-
- unsigned char cur_rx;
- unsigned char cur_pwr_dn;
-
- // If the input buffer is bypassed, we need to power it down too.
-
- bool ok = _read_9862 (codec, reg, &cur_rx);
- ok &= _read_9862 (codec, REG_RX_PWR_DN, &cur_pwr_dn);
- if (!ok)
- return false;
-
- if (bypass){
- cur_rx |= RX_X_BYPASS_INPUT_BUFFER;
- cur_pwr_dn |= ((which_adc & 1) == 0) ? RX_PWR_DN_BUF_A : RX_PWR_DN_BUF_B;
- }
- else {
- cur_rx &= ~RX_X_BYPASS_INPUT_BUFFER;
- cur_pwr_dn &= ~(((which_adc & 1) == 0) ? RX_PWR_DN_BUF_A : RX_PWR_DN_BUF_B);
- }
-
- ok &= _write_9862 (codec, reg, cur_rx);
- ok &= _write_9862 (codec, REG_RX_PWR_DN, cur_pwr_dn);
- return ok;
-}
-
-bool
-usrp_basic::set_dc_offset_cl_enable(int bits, int mask)
-{
- return _write_fpga_reg(FR_DC_OFFSET_CL_EN,
- (d_fpga_shadows[FR_DC_OFFSET_CL_EN] & ~mask) | (bits & mask));
-}
-
-// ----------------------------------------------------------------
-
-bool
-usrp_basic::_write_fpga_reg (int regno, int value)
-{
- if (d_verbose){
- fprintf (stdout, "_write_fpga_reg(%3d, 0x%08x)\n", regno, value);
- fflush (stdout);
- }
-
- if (regno >= 0 && regno < MAX_REGS)
- d_fpga_shadows[regno] = value;
-
- return usrp_write_fpga_reg (d_udh, regno, value);
-}
-
-bool
-usrp_basic::_write_fpga_reg_masked (int regno, int value, int mask)
-{
- //Only use this for registers who actually use a mask in the verilog firmware, like FR_RX_MASTER_SLAVE
- //value is a 16 bits value and mask is a 16 bits mask
- if (d_verbose){
- fprintf (stdout, "_write_fpga_reg_masked(%3d, 0x%04x,0x%04x)\n", regno, value, mask);
- fflush (stdout);
- }
-
- if (regno >= 0 && regno < MAX_REGS)
- d_fpga_shadows[regno] = value;
-
- return usrp_write_fpga_reg (d_udh, regno, (value & 0xffff) | ((mask & 0xffff)<<16));
-}
-
-
-bool
-usrp_basic::_read_fpga_reg (int regno, int *value)
-{
- return usrp_read_fpga_reg (d_udh, regno, value);
-}
-
-int
-usrp_basic::_read_fpga_reg (int regno)
-{
- int value;
- if (!_read_fpga_reg (regno, &value))
- return READ_FAILED;
- return value;
-}
-
-bool
-usrp_basic::_write_9862 (int which_codec, int regno, unsigned char value)
-{
- if (0 && d_verbose){
- // FIXME really want to enable logging in usrp_prims:usrp_9862_write
- fprintf(stdout, "_write_9862(codec = %d, regno = %2d, val = 0x%02x)\n", which_codec, regno, value);
- fflush(stdout);
- }
-
- return usrp_9862_write (d_udh, which_codec, regno, value);
-}
-
-
-bool
-usrp_basic::_read_9862 (int which_codec, int regno, unsigned char *value) const
-{
- return usrp_9862_read (d_udh, which_codec, regno, value);
-}
-
-int
-usrp_basic::_read_9862 (int which_codec, int regno) const
-{
- unsigned char value;
- if (!_read_9862 (which_codec, regno, &value))
- return READ_FAILED;
- return value;
-}
-
-bool
-usrp_basic::_write_spi (int optional_header, int enables, int format, std::string buf)
-{
- return usrp_spi_write (d_udh, optional_header, enables, format,
- buf.data(), buf.size());
-}
-
-std::string
-usrp_basic::_read_spi (int optional_header, int enables, int format, int len)
-{
- if (len <= 0)
- return "";
-
- char buf[len];
-
- if (!usrp_spi_read (d_udh, optional_header, enables, format, buf, len))
- return "";
-
- return std::string (buf, len);
-}
-
-
-bool
-usrp_basic::_set_led (int which_led, bool on)
-{
- return usrp_set_led (d_udh, which_led, on);
-}
-
-bool
-usrp_basic::write_atr_tx_delay(int value)
-{
- return _write_fpga_reg(FR_ATR_TX_DELAY, value);
-}
-
-bool
-usrp_basic::write_atr_rx_delay(int value)
-{
- return _write_fpga_reg(FR_ATR_RX_DELAY, value);
-}
-
-/*
- * ----------------------------------------------------------------
- * Routines to access and control daughterboard specific i/o
- * ----------------------------------------------------------------
- */
-static int
-slot_id_to_oe_reg (int slot_id)
-{
- static int reg[4] = { FR_OE_0, FR_OE_1, FR_OE_2, FR_OE_3 };
- assert (0 <= slot_id && slot_id < 4);
- return reg[slot_id];
-}
-
-static int
-slot_id_to_io_reg (int slot_id)
-{
- static int reg[4] = { FR_IO_0, FR_IO_1, FR_IO_2, FR_IO_3 };
- assert (0 <= slot_id && slot_id < 4);
- return reg[slot_id];
-}
-
-static int
-slot_id_to_refclk_reg(int slot_id)
-{
- static int reg[4] = { FR_TX_A_REFCLK, FR_RX_A_REFCLK, FR_TX_B_REFCLK, FR_RX_B_REFCLK };
- assert (0 <= slot_id && slot_id < 4);
- return reg[slot_id];
-}
-
-static int
-slot_id_to_atr_mask_reg(int slot_id)
-{
- static int reg[4] = { FR_ATR_MASK_0, FR_ATR_MASK_1, FR_ATR_MASK_2, FR_ATR_MASK_3 };
- assert (0 <= slot_id && slot_id < 4);
- return reg[slot_id];
-}
-
-static int
-slot_id_to_atr_txval_reg(int slot_id)
-{
- static int reg[4] = { FR_ATR_TXVAL_0, FR_ATR_TXVAL_1, FR_ATR_TXVAL_2, FR_ATR_TXVAL_3 };
- assert (0 <= slot_id && slot_id < 4);
- return reg[slot_id];
-}
-
-static int
-slot_id_to_atr_rxval_reg(int slot_id)
-{
- static int reg[4] = { FR_ATR_RXVAL_0, FR_ATR_RXVAL_1, FR_ATR_RXVAL_2, FR_ATR_RXVAL_3 };
- assert (0 <= slot_id && slot_id < 4);
- return reg[slot_id];
-}
-
-static int
-to_slot(txrx_t txrx, int which_side)
-{
- // TX_A = 0
- // RX_A = 1
- // TX_B = 2
- // RX_B = 3
- return ((which_side & 0x1) << 1) | ((txrx & 0x1) == C_RX);
-}
-
-bool
-usrp_basic::common_set_pga(txrx_t txrx, int which_amp, double gain)
-{
- if (which_amp < 0 || which_amp > 3)
- return false;
-
- gain = std::min(common_pga_max(txrx),
- std::max(common_pga_min(txrx), gain));
-
- int codec = which_amp >> 1;
- int int_gain = (int) rint((gain - common_pga_min(txrx)) / common_pga_db_per_step(txrx));
-
- if (txrx == C_TX){ // 0 and 1 are same, as are 2 and 3
- return _write_9862(codec, REG_TX_PGA, int_gain);
- }
- else {
- int reg = (which_amp & 1) == 0 ? REG_RX_A : REG_RX_B;
-
- // read current value to get input buffer bypass flag.
- unsigned char cur_rx;
- if (!_read_9862(codec, reg, &cur_rx))
- return false;
-
- cur_rx = (cur_rx & RX_X_BYPASS_INPUT_BUFFER) | (int_gain & 0x7f);
- return _write_9862(codec, reg, cur_rx);
- }
-}
-
-double
-usrp_basic::common_pga(txrx_t txrx, int which_amp) const
-{
- if (which_amp < 0 || which_amp > 3)
- return READ_FAILED;
-
- if (txrx == C_TX){
- int codec = which_amp >> 1;
- unsigned char v;
- bool ok = _read_9862 (codec, REG_TX_PGA, &v);
- if (!ok)
- return READ_FAILED;
-
- return (pga_db_per_step() * v) + pga_min();
- }
- else {
- int codec = which_amp >> 1;
- int reg = (which_amp & 1) == 0 ? REG_RX_A : REG_RX_B;
- unsigned char v;
- bool ok = _read_9862 (codec, reg, &v);
- if (!ok)
- return READ_FAILED;
-
- return (pga_db_per_step() * (v & 0x1f)) + pga_min();
- }
-}
-
-double
-usrp_basic::common_pga_min(txrx_t txrx) const
-{
- if (txrx == C_TX)
- return -20.0;
- else
- return 0.0;
-}
-
-double
-usrp_basic::common_pga_max(txrx_t txrx) const
-{
- if (txrx == C_TX)
- return 0.0;
- else
- return 20.0;
-}
-
-double
-usrp_basic::common_pga_db_per_step(txrx_t txrx) const
-{
- if (txrx == C_TX)
- return 20.0 / 255;
- else
- return 20.0 / 20;
-}
-
-bool
-usrp_basic::_common_write_oe(txrx_t txrx, int which_side, int value, int mask)
-{
- if (! (0 <= which_side && which_side <= 1))
- return false;
-
- return _write_fpga_reg(slot_id_to_oe_reg(to_slot(txrx, which_side)),
- (mask << 16) | (value & 0xffff));
-}
-
-bool
-usrp_basic::common_write_io(txrx_t txrx, int which_side, int value, int mask)
-{
- if (! (0 <= which_side && which_side <= 1))
- return false;
-
- return _write_fpga_reg(slot_id_to_io_reg(to_slot(txrx, which_side)),
- (mask << 16) | (value & 0xffff));
-}
-
-bool
-usrp_basic::common_read_io(txrx_t txrx, int which_side, int *value)
-{
- if (! (0 <= which_side && which_side <= 1))
- return false;
-
- int t;
- int reg = which_side + 1; // FIXME, *very* magic number (fix in serial_io.v)
- bool ok = _read_fpga_reg(reg, &t);
- if (!ok)
- return false;
-
- if (txrx == C_TX){
- *value = t & 0xffff; // FIXME, more magic
- return true;
- }
- else {
- *value = (t >> 16) & 0xffff; // FIXME, more magic
- return true;
- }
-}
-
-int
-usrp_basic::common_read_io(txrx_t txrx, int which_side)
-{
- int value;
- if (!common_read_io(txrx, which_side, &value))
- return READ_FAILED;
- return value;
-}
-
-bool
-usrp_basic::common_write_refclk(txrx_t txrx, int which_side, int value)
-{
- if (! (0 <= which_side && which_side <= 1))
- return false;
-
- return _write_fpga_reg(slot_id_to_refclk_reg(to_slot(txrx, which_side)),
- value);
-}
-
-bool
-usrp_basic::common_write_atr_mask(txrx_t txrx, int which_side, int value)
-{
- if (! (0 <= which_side && which_side <= 1))
- return false;
-
- return _write_fpga_reg(slot_id_to_atr_mask_reg(to_slot(txrx, which_side)),
- value);
-}
-
-bool
-usrp_basic::common_write_atr_txval(txrx_t txrx, int which_side, int value)
-{
- if (! (0 <= which_side && which_side <= 1))
- return false;
-
- return _write_fpga_reg(slot_id_to_atr_txval_reg(to_slot(txrx, which_side)),
- value);
-}
-
-bool
-usrp_basic::common_write_atr_rxval(txrx_t txrx, int which_side, int value)
-{
- if (! (0 <= which_side && which_side <= 1))
- return false;
-
- return _write_fpga_reg(slot_id_to_atr_rxval_reg(to_slot(txrx, which_side)),
- value);
-}
-
-bool
-usrp_basic::common_write_aux_dac(txrx_t txrx, int which_side, int which_dac, int value)
-{
- return _write_aux_dac(to_slot(txrx, which_side), which_dac, value);
-}
-
-bool
-usrp_basic::common_read_aux_adc(txrx_t txrx, int which_side, int which_adc, int *value)
-{
- return _read_aux_adc(to_slot(txrx, which_side), which_adc, value);
-}
-
-int
-usrp_basic::common_read_aux_adc(txrx_t txrx, int which_side, int which_adc)
-{
- return _read_aux_adc(to_slot(txrx, which_side), which_adc);
-}
-
-
-////////////////////////////////////////////////////////////////
-//
-// usrp_basic_rx
-//
-////////////////////////////////////////////////////////////////
-
-static unsigned char rx_init_regs[] = {
- REG_RX_PWR_DN, 0,
- REG_RX_A, 0, // minimum gain = 0x00 (max gain = 0x14)
- REG_RX_B, 0, // minimum gain = 0x00 (max gain = 0x14)
- REG_RX_MISC, (RX_MISC_HS_DUTY_CYCLE | RX_MISC_CLK_DUTY),
- REG_RX_IF, (RX_IF_USE_CLKOUT1
- | RX_IF_2S_COMP),
- REG_RX_DIGITAL, (RX_DIGITAL_2_CHAN)
-};
-
-
-usrp_basic_rx::usrp_basic_rx (int which_board, int fusb_block_size, int fusb_nblocks,
- const std::string fpga_filename,
- const std::string firmware_filename
- )
- : usrp_basic (which_board, open_rx_interface, fpga_filename, firmware_filename),
- d_devhandle (0), d_ephandle (0),
- d_bytes_seen (0), d_first_read (true),
- d_rx_enable (false)
-{
- // initialize rx specific registers
-
- if (!usrp_9862_write_many_all (d_udh, rx_init_regs, sizeof (rx_init_regs))){
- fprintf (stderr, "usrp_basic_rx: failed to init AD9862 RX regs\n");
- throw std::runtime_error ("usrp_basic_rx/init_9862");
- }
-
- if (0){
- // FIXME power down 2nd codec rx path
- usrp_9862_write (d_udh, 1, REG_RX_PWR_DN, 0x1); // power down everything
- }
-
- // Reset the rx path and leave it disabled.
- set_rx_enable (false);
- usrp_set_fpga_rx_reset (d_udh, true);
- usrp_set_fpga_rx_reset (d_udh, false);
-
- set_fpga_rx_sample_rate_divisor (2); // usually correct
-
- set_dc_offset_cl_enable(0xf, 0xf); // enable DC offset removal control loops
-
- probe_rx_slots (false);
-
- //d_db[0] = instantiate_dbs(d_dbid[0], this, 0);
- //d_db[1] = instantiate_dbs(d_dbid[1], this, 1);
-
- // check fusb buffering parameters
-
- if (fusb_block_size < 0 || fusb_block_size > FUSB_BLOCK_SIZE)
- throw std::out_of_range ("usrp_basic_rx: invalid fusb_block_size");
-
- if (fusb_nblocks < 0)
- throw std::out_of_range ("usrp_basic_rx: invalid fusb_nblocks");
-
- if (fusb_block_size == 0)
- fusb_block_size = fusb_sysconfig::default_block_size();
-
- if (fusb_nblocks == 0)
- fusb_nblocks = std::max (1, FUSB_BUFFER_SIZE / fusb_block_size);
-
- d_devhandle = fusb_sysconfig::make_devhandle (d_udh, d_ctx);
- d_ephandle = d_devhandle->make_ephandle (USRP_RX_ENDPOINT, true,
- fusb_block_size, fusb_nblocks);
-
- write_atr_mask(0, 0); // zero Rx A Auto Transmit/Receive regs
- write_atr_txval(0, 0);
- write_atr_rxval(0, 0);
- write_atr_mask(1, 0); // zero Rx B Auto Transmit/Receive regs
- write_atr_txval(1, 0);
- write_atr_rxval(1, 0);
-}
-
-static unsigned char rx_fini_regs[] = {
- REG_RX_PWR_DN, 0x1 // power down everything
-};
-
-usrp_basic_rx::~usrp_basic_rx ()
-{
- if (!set_rx_enable (false)){
- fprintf (stderr, "usrp_basic_rx: set_fpga_rx_enable failed\n");
- }
-
- d_ephandle->stop ();
- delete d_ephandle;
- delete d_devhandle;
-
- if (!usrp_9862_write_many_all (d_udh, rx_fini_regs, sizeof (rx_fini_regs))){
- fprintf (stderr, "usrp_basic_rx: failed to fini AD9862 RX regs\n");
- }
-
- shutdown_daughterboards();
-}
-
-
-bool
-usrp_basic_rx::start ()
-{
- if (!usrp_basic::start ()) // invoke parent's method
- return false;
-
- // fire off reads before asserting rx_enable
-
- if (!d_ephandle->start ()){
- fprintf (stderr, "usrp_basic_rx: failed to start end point streaming");
- return false;
- }
-
- if (!set_rx_enable (true)){
- fprintf (stderr, "usrp_basic_rx: set_rx_enable failed\n");
- return false;
- }
-
- return true;
-}
-
-bool
-usrp_basic_rx::stop ()
-{
- bool ok = usrp_basic::stop();
-
- if (!set_rx_enable(false)){
- fprintf (stderr, "usrp_basic_rx: set_rx_enable(false) failed\n");
- ok = false;
- }
-
- if (!d_ephandle->stop()){
- fprintf (stderr, "usrp_basic_rx: failed to stop end point streaming");
- ok = false;
- }
-
- return ok;
-}
-
-usrp_basic_rx *
-usrp_basic_rx::make (int which_board, int fusb_block_size, int fusb_nblocks,
- const std::string fpga_filename,
- const std::string firmware_filename)
-{
- usrp_basic_rx *u = 0;
-
- try {
- u = new usrp_basic_rx (which_board, fusb_block_size, fusb_nblocks,
- fpga_filename, firmware_filename);
- return u;
- }
- catch (...){
- delete u;
- return 0;
- }
-
- return u;
-}
-
-bool
-usrp_basic_rx::set_fpga_rx_sample_rate_divisor (unsigned int div)
-{
- return _write_fpga_reg (FR_RX_SAMPLE_RATE_DIV, div - 1);
-}
-
-
-/*
- * \brief read data from the D/A's via the FPGA.
- * \p len must be a multiple of 512 bytes.
- *
- * \returns the number of bytes read, or -1 on error.
- *
- * If overrun is non-NULL it will be set true iff an RX overrun is detected.
- */
-int
-usrp_basic_rx::read (void *buf, int len, bool *overrun)
-{
- int r;
-
- if (overrun)
- *overrun = false;
-
- if (len < 0 || (len % 512) != 0){
- fprintf (stderr, "usrp_basic_rx::read: invalid length = %d\n", len);
- return -1;
- }
-
- r = d_ephandle->read (buf, len);
- if (r > 0)
- d_bytes_seen += r;
-
- /*
- * In many cases, the FPGA reports an rx overrun right after we
- * enable the Rx path. If this is our first read, check for the
- * overrun to clear the condition, then ignore the result.
- */
- if (0 && d_first_read){ // FIXME
- d_first_read = false;
- bool bogus_overrun;
- usrp_check_rx_overrun (d_udh, &bogus_overrun);
- }
-
- if (overrun != 0 && d_bytes_seen >= d_bytes_per_poll){
- d_bytes_seen = 0;
- if (!usrp_check_rx_overrun (d_udh, overrun)){
- fprintf (stderr, "usrp_basic_rx: usrp_check_rx_overrun failed\n");
- }
- }
-
- return r;
-}
-
-bool
-usrp_basic_rx::set_rx_enable (bool on)
-{
- d_rx_enable = on;
- return usrp_set_fpga_rx_enable (d_udh, on);
-}
-
-// conditional disable, return prev state
-bool
-usrp_basic_rx::disable_rx ()
-{
- bool enabled = rx_enable ();
- if (enabled)
- set_rx_enable (false);
- return enabled;
-}
-
-// conditional set
-void
-usrp_basic_rx::restore_rx (bool on)
-{
- if (on != rx_enable ())
- set_rx_enable (on);
-}
-
-void
-usrp_basic_rx::probe_rx_slots (bool verbose)
-{
- struct usrp_dboard_eeprom eeprom;
- static int slot_id_map[2] = { SLOT_RX_A, SLOT_RX_B };
- static const char *slot_name[2] = { "RX d'board A", "RX d'board B" };
-
- for (int i = 0; i < 2; i++){
- int slot_id = slot_id_map [i];
- const char *msg = 0;
- usrp_dbeeprom_status_t s = usrp_read_dboard_eeprom (d_udh, slot_id, &eeprom);
-
- switch (s){
- case UDBE_OK:
- d_dbid[i] = eeprom.id;
- msg = usrp_dbid_to_string (eeprom.id).c_str ();
- set_adc_offset (2*i+0, eeprom.offset[0]);
- set_adc_offset (2*i+1, eeprom.offset[1]);
- _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | eeprom.oe);
- _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
- break;
-
- case UDBE_NO_EEPROM:
- d_dbid[i] = -1;
- msg = "<none>";
- _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
- _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
- break;
-
- case UDBE_INVALID_EEPROM:
- d_dbid[i] = -2;
- msg = "Invalid EEPROM contents";
- _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
- _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
- break;
-
- case UDBE_BAD_SLOT:
- default:
- assert (0);
- }
-
- if (verbose){
- fflush (stdout);
- fprintf (stderr, "%s: %s\n", slot_name[i], msg);
- }
- }
-}
-
-bool
-usrp_basic_rx::set_pga (int which_amp, double gain)
-{
- return common_set_pga(C_RX, which_amp, gain);
-}
-
-double
-usrp_basic_rx::pga(int which_amp) const
-{
- return common_pga(C_RX, which_amp);
-}
-
-double
-usrp_basic_rx::pga_min() const
-{
- return common_pga_min(C_RX);
-}
-
-double
-usrp_basic_rx::pga_max() const
-{
- return common_pga_max(C_RX);
-}
-
-double
-usrp_basic_rx::pga_db_per_step() const
-{
- return common_pga_db_per_step(C_RX);
-}
-
-bool
-usrp_basic_rx::_write_oe (int which_side, int value, int mask)
-{
- return _common_write_oe(C_RX, which_side, value, mask);
-}
-
-bool
-usrp_basic_rx::write_io (int which_side, int value, int mask)
-{
- return common_write_io(C_RX, which_side, value, mask);
-}
-
-bool
-usrp_basic_rx::read_io (int which_side, int *value)
-{
- return common_read_io(C_RX, which_side, value);
-}
-
-int
-usrp_basic_rx::read_io (int which_side)
-{
- return common_read_io(C_RX, which_side);
-}
-
-bool
-usrp_basic_rx::write_refclk(int which_side, int value)
-{
- return common_write_refclk(C_RX, which_side, value);
-}
-
-bool
-usrp_basic_rx::write_atr_mask(int which_side, int value)
-{
- return common_write_atr_mask(C_RX, which_side, value);
-}
-
-bool
-usrp_basic_rx::write_atr_txval(int which_side, int value)
-{
- return common_write_atr_txval(C_RX, which_side, value);
-}
-
-bool
-usrp_basic_rx::write_atr_rxval(int which_side, int value)
-{
- return common_write_atr_rxval(C_RX, which_side, value);
-}
-
-bool
-usrp_basic_rx::write_aux_dac (int which_side, int which_dac, int value)
-{
- return common_write_aux_dac(C_RX, which_side, which_dac, value);
-}
-
-bool
-usrp_basic_rx::read_aux_adc (int which_side, int which_adc, int *value)
-{
- return common_read_aux_adc(C_RX, which_side, which_adc, value);
-}
-
-int
-usrp_basic_rx::read_aux_adc (int which_side, int which_adc)
-{
- return common_read_aux_adc(C_RX, which_side, which_adc);
-}
-
-int
-usrp_basic_rx::block_size () const { return d_ephandle->block_size(); }
-
-////////////////////////////////////////////////////////////////
-//
-// usrp_basic_tx
-//
-////////////////////////////////////////////////////////////////
-
-
-//
-// DAC input rate 64 MHz interleaved for a total input rate of 128 MHz
-// DAC input is latched on rising edge of CLKOUT2
-// NCO is disabled
-// interpolate 2x
-// coarse modulator disabled
-//
-
-static unsigned char tx_init_regs[] = {
- REG_TX_PWR_DN, 0,
- REG_TX_A_OFFSET_LO, 0,
- REG_TX_A_OFFSET_HI, 0,
- REG_TX_B_OFFSET_LO, 0,
- REG_TX_B_OFFSET_HI, 0,
- REG_TX_A_GAIN, (TX_X_GAIN_COARSE_FULL | 0),
- REG_TX_B_GAIN, (TX_X_GAIN_COARSE_FULL | 0),
- REG_TX_PGA, 0xff, // maximum gain (0 dB)
- REG_TX_MISC, 0,
- REG_TX_IF, (TX_IF_USE_CLKOUT1
- | TX_IF_I_FIRST
- | TX_IF_INV_TX_SYNC
- | TX_IF_2S_COMP
- | TX_IF_INTERLEAVED),
- REG_TX_DIGITAL, (TX_DIGITAL_2_DATA_PATHS
- | TX_DIGITAL_INTERPOLATE_4X),
- REG_TX_MODULATOR, (TX_MODULATOR_DISABLE_NCO
- | TX_MODULATOR_COARSE_MODULATION_NONE),
- REG_TX_NCO_FTW_7_0, 0,
- REG_TX_NCO_FTW_15_8, 0,
- REG_TX_NCO_FTW_23_16, 0
-};
-
-usrp_basic_tx::usrp_basic_tx (int which_board, int fusb_block_size, int fusb_nblocks,
- const std::string fpga_filename,
- const std::string firmware_filename)
- : usrp_basic (which_board, open_tx_interface, fpga_filename, firmware_filename),
- d_devhandle (0), d_ephandle (0),
- d_bytes_seen (0), d_first_write (true),
- d_tx_enable (false)
-{
- if (!usrp_9862_write_many_all (d_udh, tx_init_regs, sizeof (tx_init_regs))){
- fprintf (stderr, "usrp_basic_tx: failed to init AD9862 TX regs\n");
- throw std::runtime_error ("usrp_basic_tx/init_9862");
- }
-
- if (0){
- // FIXME power down 2nd codec tx path
- usrp_9862_write (d_udh, 1, REG_TX_PWR_DN,
- (TX_PWR_DN_TX_DIGITAL
- | TX_PWR_DN_TX_ANALOG_BOTH));
- }
-
- // Reset the tx path and leave it disabled.
- set_tx_enable (false);
- usrp_set_fpga_tx_reset (d_udh, true);
- usrp_set_fpga_tx_reset (d_udh, false);
-
- set_fpga_tx_sample_rate_divisor (4); // we're using interp x4
-
- probe_tx_slots (false);
-
- //d_db[0] = instantiate_dbs(d_dbid[0], this, 0);
- //d_db[1] = instantiate_dbs(d_dbid[1], this, 1);
-
- // check fusb buffering parameters
-
- if (fusb_block_size < 0 || fusb_block_size > FUSB_BLOCK_SIZE)
- throw std::out_of_range ("usrp_basic_rx: invalid fusb_block_size");
-
- if (fusb_nblocks < 0)
- throw std::out_of_range ("usrp_basic_rx: invalid fusb_nblocks");
-
- if (fusb_block_size == 0)
- fusb_block_size = FUSB_BLOCK_SIZE;
-
- if (fusb_nblocks == 0)
- fusb_nblocks = std::max (1, FUSB_BUFFER_SIZE / fusb_block_size);
-
- d_devhandle = fusb_sysconfig::make_devhandle (d_udh, d_ctx);
- d_ephandle = d_devhandle->make_ephandle (USRP_TX_ENDPOINT, false,
- fusb_block_size, fusb_nblocks);
-
- write_atr_mask(0, 0); // zero Tx A Auto Transmit/Receive regs
- write_atr_txval(0, 0);
- write_atr_rxval(0, 0);
- write_atr_mask(1, 0); // zero Tx B Auto Transmit/Receive regs
- write_atr_txval(1, 0);
- write_atr_rxval(1, 0);
-}
-
-
-static unsigned char tx_fini_regs[] = {
- REG_TX_PWR_DN, (TX_PWR_DN_TX_DIGITAL
- | TX_PWR_DN_TX_ANALOG_BOTH),
- REG_TX_MODULATOR, (TX_MODULATOR_DISABLE_NCO
- | TX_MODULATOR_COARSE_MODULATION_NONE)
-};
-
-usrp_basic_tx::~usrp_basic_tx ()
-{
- d_ephandle->stop ();
- delete d_ephandle;
- delete d_devhandle;
-
- if (!usrp_9862_write_many_all (d_udh, tx_fini_regs, sizeof (tx_fini_regs))){
- fprintf (stderr, "usrp_basic_tx: failed to fini AD9862 TX regs\n");
- }
-
- shutdown_daughterboards();
-}
-
-bool
-usrp_basic_tx::start ()
-{
- if (!usrp_basic::start ())
- return false;
-
- if (!set_tx_enable (true)){
- fprintf (stderr, "usrp_basic_tx: set_tx_enable failed\n");
- return false;
- }
-
- if (!d_ephandle->start ()){
- fprintf (stderr, "usrp_basic_tx: failed to start end point streaming");
- return false;
- }
-
- return true;
-}
-
-bool
-usrp_basic_tx::stop ()
-{
- bool ok = usrp_basic::stop ();
-
- if (!d_ephandle->stop ()){
- fprintf (stderr, "usrp_basic_tx: failed to stop end point streaming");
- ok = false;
- }
-
- if (!set_tx_enable (false)){
- fprintf (stderr, "usrp_basic_tx: set_tx_enable(false) failed\n");
- ok = false;
- }
-
- return ok;
-}
-
-usrp_basic_tx *
-usrp_basic_tx::make (int which_board, int fusb_block_size, int fusb_nblocks,
- const std::string fpga_filename,
- const std::string firmware_filename)
-{
- usrp_basic_tx *u = 0;
-
- try {
- u = new usrp_basic_tx (which_board, fusb_block_size, fusb_nblocks,
- fpga_filename, firmware_filename);
- return u;
- }
- catch (...){
- delete u;
- return 0;
- }
-
- return u;
-}
-
-bool
-usrp_basic_tx::set_fpga_tx_sample_rate_divisor (unsigned int div)
-{
- return _write_fpga_reg (FR_TX_SAMPLE_RATE_DIV, div - 1);
-}
-
-/*!
- * \brief Write data to the A/D's via the FPGA.
- *
- * \p len must be a multiple of 512 bytes.
- * \returns number of bytes written or -1 on error.
- *
- * if \p underrun is non-NULL, it will be set to true iff
- * a transmit underrun condition is detected.
- */
-int
-usrp_basic_tx::write (const void *buf, int len, bool *underrun)
-{
- int r;
-
- if (underrun)
- *underrun = false;
-
- if (len < 0 || (len % 512) != 0){
- fprintf (stderr, "usrp_basic_tx::write: invalid length = %d\n", len);
- return -1;
- }
-
- r = d_ephandle->write (buf, len);
- if (r > 0)
- d_bytes_seen += r;
-
- /*
- * In many cases, the FPGA reports an tx underrun right after we
- * enable the Tx path. If this is our first write, check for the
- * underrun to clear the condition, then ignore the result.
- */
- if (d_first_write && d_bytes_seen >= 4 * FUSB_BLOCK_SIZE){
- d_first_write = false;
- bool bogus_underrun;
- usrp_check_tx_underrun (d_udh, &bogus_underrun);
- }
-
- if (underrun != 0 && d_bytes_seen >= d_bytes_per_poll){
- d_bytes_seen = 0;
- if (!usrp_check_tx_underrun (d_udh, underrun)){
- fprintf (stderr, "usrp_basic_tx: usrp_check_tx_underrun failed\n");
- }
- }
-
- return r;
-}
-
-void
-usrp_basic_tx::wait_for_completion ()
-{
- d_ephandle->wait_for_completion ();
-}
-
-bool
-usrp_basic_tx::set_tx_enable (bool on)
-{
- d_tx_enable = on;
- // fprintf (stderr, "set_tx_enable %d\n", on);
- return usrp_set_fpga_tx_enable (d_udh, on);
-}
-
-// conditional disable, return prev state
-bool
-usrp_basic_tx::disable_tx ()
-{
- bool enabled = tx_enable ();
- if (enabled)
- set_tx_enable (false);
- return enabled;
-}
-
-// conditional set
-void
-usrp_basic_tx::restore_tx (bool on)
-{
- if (on != tx_enable ())
- set_tx_enable (on);
-}
-
-void
-usrp_basic_tx::probe_tx_slots (bool verbose)
-{
- struct usrp_dboard_eeprom eeprom;
- static int slot_id_map[2] = { SLOT_TX_A, SLOT_TX_B };
- static const char *slot_name[2] = { "TX d'board A", "TX d'board B" };
-
- for (int i = 0; i < 2; i++){
- int slot_id = slot_id_map [i];
- const char *msg = 0;
- usrp_dbeeprom_status_t s = usrp_read_dboard_eeprom (d_udh, slot_id, &eeprom);
-
- switch (s){
- case UDBE_OK:
- d_dbid[i] = eeprom.id;
- msg = usrp_dbid_to_string (eeprom.id).c_str ();
- // FIXME, figure out interpretation of dc offset for TX d'boards
- // offset = (eeprom.offset[1] << 16) | (eeprom.offset[0] & 0xffff);
- _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | eeprom.oe);
- _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
- break;
-
- case UDBE_NO_EEPROM:
- d_dbid[i] = -1;
- msg = "<none>";
- _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
- _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
- break;
-
- case UDBE_INVALID_EEPROM:
- d_dbid[i] = -2;
- msg = "Invalid EEPROM contents";
- _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
- _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
- break;
-
- case UDBE_BAD_SLOT:
- default:
- assert (0);
- }
-
- if (verbose){
- fflush (stdout);
- fprintf (stderr, "%s: %s\n", slot_name[i], msg);
- }
- }
-}
-
-bool
-usrp_basic_tx::set_pga (int which_amp, double gain)
-{
- return common_set_pga(C_TX, which_amp, gain);
-}
-
-double
-usrp_basic_tx::pga (int which_amp) const
-{
- return common_pga(C_TX, which_amp);
-}
-
-double
-usrp_basic_tx::pga_min() const
-{
- return common_pga_min(C_TX);
-}
-
-double
-usrp_basic_tx::pga_max() const
-{
- return common_pga_max(C_TX);
-}
-
-double
-usrp_basic_tx::pga_db_per_step() const
-{
- return common_pga_db_per_step(C_TX);
-}
-
-bool
-usrp_basic_tx::_write_oe (int which_side, int value, int mask)
-{
- return _common_write_oe(C_TX, which_side, value, mask);
-}
-
-bool
-usrp_basic_tx::write_io (int which_side, int value, int mask)
-{
- return common_write_io(C_TX, which_side, value, mask);
-}
-
-bool
-usrp_basic_tx::read_io (int which_side, int *value)
-{
- return common_read_io(C_TX, which_side, value);
-}
-
-int
-usrp_basic_tx::read_io (int which_side)
-{
- return common_read_io(C_TX, which_side);
-}
-
-bool
-usrp_basic_tx::write_refclk(int which_side, int value)
-{
- return common_write_refclk(C_TX, which_side, value);
-}
-
-bool
-usrp_basic_tx::write_atr_mask(int which_side, int value)
-{
- return common_write_atr_mask(C_TX, which_side, value);
-}
-
-bool
-usrp_basic_tx::write_atr_txval(int which_side, int value)
-{
- return common_write_atr_txval(C_TX, which_side, value);
-}
-
-bool
-usrp_basic_tx::write_atr_rxval(int which_side, int value)
-{
- return common_write_atr_rxval(C_TX, which_side, value);
-}
-
-bool
-usrp_basic_tx::write_aux_dac (int which_side, int which_dac, int value)
-{
- return common_write_aux_dac(C_TX, which_side, which_dac, value);
-}
-
-bool
-usrp_basic_tx::read_aux_adc (int which_side, int which_adc, int *value)
-{
- return common_read_aux_adc(C_TX, which_side, which_adc, value);
-}
-
-int
-usrp_basic_tx::read_aux_adc (int which_side, int which_adc)
-{
- return common_read_aux_adc(C_TX, which_side, which_adc);
-}
-
-int
-usrp_basic_tx::block_size () const { return d_ephandle->block_size(); }
-
--- /dev/null
+/* -*- c++ -*- */
+/*
+ * Copyright 2003,2004,2008,2009 Free Software Foundation, Inc.
+ *
+ * This file is part of GNU Radio
+ *
+ * GNU Radio is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3, or (at your option)
+ * any later version.
+ *
+ * GNU Radio is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with GNU Radio; see the file COPYING. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <usrp/usrp_basic.h>
+#include "usrp/usrp_prims.h"
+#include "usrp_interfaces.h"
+#include "fpga_regs_common.h"
+#include "fpga_regs_standard.h"
+#include "fusb.h"
+#include "db_boards.h"
+#include <stdexcept>
+#include <assert.h>
+#include <math.h>
+#include <ad9862.h>
+#include <string.h>
+#include <cstdio>
+
+#if 1
+#include <usb.h>
+#else
+#include <libusb-1.0/libusb.h>
+#endif
+
+using namespace ad9862;
+
+#define NELEM(x) (sizeof (x) / sizeof (x[0]))
+
+// These set the buffer size used for each end point using the fast
+// usb interface. The kernel ends up locking down this much memory.
+
+static const int FUSB_BUFFER_SIZE = fusb_sysconfig::default_buffer_size();
+static const int FUSB_BLOCK_SIZE = fusb_sysconfig::max_block_size();
+static const int FUSB_NBLOCKS = FUSB_BUFFER_SIZE / FUSB_BLOCK_SIZE;
+
+
+static const double POLLING_INTERVAL = 0.1; // seconds
+
+////////////////////////////////////////////////////////////////
+
+static libusb_device_handle *
+open_rx_interface (libusb_device *dev)
+{
+ libusb_device_handle *udh = usrp_open_rx_interface (dev);
+ if (udh == 0){
+ fprintf (stderr, "usrp_basic_rx: can't open rx interface\n");
+ }
+ return udh;
+}
+
+static libusb_device_handle *
+open_tx_interface (libusb_device *dev)
+{
+ libusb_device_handle *udh = usrp_open_tx_interface (dev);
+ if (udh == 0){
+ fprintf (stderr, "usrp_basic_tx: can't open tx interface\n");
+ }
+ return udh;
+}
+
+
+//////////////////////////////////////////////////////////////////
+//
+// usrp_basic
+//
+////////////////////////////////////////////////////////////////
+
+
+// Given:
+// CLKIN = 64 MHz
+// CLKSEL pin = high
+//
+// These settings give us:
+// CLKOUT1 = CLKIN = 64 MHz
+// CLKOUT2 = CLKIN = 64 MHz
+// ADC is clocked at 64 MHz
+// DAC is clocked at 128 MHz
+
+static unsigned char common_regs[] = {
+ REG_GENERAL, 0,
+ REG_DLL, (DLL_DISABLE_INTERNAL_XTAL_OSC
+ | DLL_MULT_2X
+ | DLL_FAST),
+ REG_CLKOUT, CLKOUT2_EQ_DLL_OVER_2,
+ REG_AUX_ADC_CLK, AUX_ADC_CLK_CLK_OVER_4
+};
+
+void
+usrp_basic::shutdown_daughterboards()
+{
+ // nuke d'boards before we close down USB in ~usrp_basic
+ // shutdown() will do any board shutdown while the USRP can still
+ // be talked to
+ for(size_t i = 0; i < d_db.size(); i++)
+ for(size_t j = 0; j < d_db[i].size(); j++)
+ d_db[i][j]->shutdown();
+}
+
+void
+usrp_basic::init_db(usrp_basic_sptr u)
+{
+ if (u.get() != this)
+ throw std::invalid_argument("u is not this");
+
+ d_db[0] = instantiate_dbs(d_dbid[0], u, 0);
+ d_db[1] = instantiate_dbs(d_dbid[1], u, 1);
+}
+
+std::vector<db_base_sptr>
+usrp_basic::db(int which_side)
+{
+ which_side &= 0x1; // clamp it to avoid any reporting any errors
+ return d_db[which_side];
+}
+
+bool
+usrp_basic::is_valid(const usrp_subdev_spec &ss)
+{
+ if (ss.side < 0 || ss.side > 1)
+ return false;
+
+ if (ss.subdev < 0 || ss.subdev >= d_db[ss.side].size())
+ return false;
+
+ return true;
+}
+
+db_base_sptr
+usrp_basic::selected_subdev(const usrp_subdev_spec &ss)
+{
+ if (!is_valid(ss))
+ throw std::invalid_argument("invalid subdev_spec");
+
+ return d_db[ss.side][ss.subdev];
+}
+
+bool
+usrp_basic::start ()
+{
+ return true; // nop
+}
+
+bool
+usrp_basic::stop ()
+{
+ return true; // nop
+}
+
+void
+usrp_basic::set_usb_data_rate (int usb_data_rate)
+{
+ d_usb_data_rate = usb_data_rate;
+ d_bytes_per_poll = (int) (usb_data_rate * POLLING_INTERVAL);
+}
+
+bool
+usrp_basic::_write_aux_dac (int slot, int which_dac, int value)
+{
+ return usrp_write_aux_dac (d_udh, slot, which_dac, value);
+}
+
+bool
+usrp_basic::_read_aux_adc (int slot, int which_adc, int *value)
+{
+ return usrp_read_aux_adc (d_udh, slot, which_adc, value);
+}
+
+int
+usrp_basic::_read_aux_adc (int slot, int which_adc)
+{
+ int value;
+ if (!_read_aux_adc (slot, which_adc, &value))
+ return READ_FAILED;
+
+ return value;
+}
+
+bool
+usrp_basic::write_eeprom (int i2c_addr, int eeprom_offset, const std::string buf)
+{
+ return usrp_eeprom_write (d_udh, i2c_addr, eeprom_offset, buf.data (), buf.size ());
+}
+
+std::string
+usrp_basic::read_eeprom (int i2c_addr, int eeprom_offset, int len)
+{
+ if (len <= 0)
+ return "";
+
+ char buf[len];
+
+ if (!usrp_eeprom_read (d_udh, i2c_addr, eeprom_offset, buf, len))
+ return "";
+
+ return std::string (buf, len);
+}
+
+bool
+usrp_basic::write_i2c (int i2c_addr, const std::string buf)
+{
+ return usrp_i2c_write (d_udh, i2c_addr, buf.data (), buf.size ());
+}
+
+std::string
+usrp_basic::read_i2c (int i2c_addr, int len)
+{
+ if (len <= 0)
+ return "";
+
+ char buf[len];
+
+ if (!usrp_i2c_read (d_udh, i2c_addr, buf, len))
+ return "";
+
+ return std::string (buf, len);
+}
+
+std::string
+usrp_basic::serial_number()
+{
+ return usrp_serial_number(d_udh);
+}
+
+// ----------------------------------------------------------------
+
+bool
+usrp_basic::set_adc_offset (int which_adc, int offset)
+{
+ if (which_adc < 0 || which_adc > 3)
+ return false;
+
+ return _write_fpga_reg (FR_ADC_OFFSET_0 + which_adc, offset);
+}
+
+bool
+usrp_basic::set_dac_offset (int which_dac, int offset, int offset_pin)
+{
+ if (which_dac < 0 || which_dac > 3)
+ return false;
+
+ int which_codec = which_dac >> 1;
+ int tx_a = (which_dac & 0x1) == 0;
+ int lo = ((offset & 0x3) << 6) | (offset_pin & 0x1);
+ int hi = (offset >> 2);
+ bool ok;
+
+ if (tx_a){
+ ok = _write_9862 (which_codec, REG_TX_A_OFFSET_LO, lo);
+ ok &= _write_9862 (which_codec, REG_TX_A_OFFSET_HI, hi);
+ }
+ else {
+ ok = _write_9862 (which_codec, REG_TX_B_OFFSET_LO, lo);
+ ok &= _write_9862 (which_codec, REG_TX_B_OFFSET_HI, hi);
+ }
+ return ok;
+}
+
+bool
+usrp_basic::set_adc_buffer_bypass (int which_adc, bool bypass)
+{
+ if (which_adc < 0 || which_adc > 3)
+ return false;
+
+ int codec = which_adc >> 1;
+ int reg = (which_adc & 1) == 0 ? REG_RX_A : REG_RX_B;
+
+ unsigned char cur_rx;
+ unsigned char cur_pwr_dn;
+
+ // If the input buffer is bypassed, we need to power it down too.
+
+ bool ok = _read_9862 (codec, reg, &cur_rx);
+ ok &= _read_9862 (codec, REG_RX_PWR_DN, &cur_pwr_dn);
+ if (!ok)
+ return false;
+
+ if (bypass){
+ cur_rx |= RX_X_BYPASS_INPUT_BUFFER;
+ cur_pwr_dn |= ((which_adc & 1) == 0) ? RX_PWR_DN_BUF_A : RX_PWR_DN_BUF_B;
+ }
+ else {
+ cur_rx &= ~RX_X_BYPASS_INPUT_BUFFER;
+ cur_pwr_dn &= ~(((which_adc & 1) == 0) ? RX_PWR_DN_BUF_A : RX_PWR_DN_BUF_B);
+ }
+
+ ok &= _write_9862 (codec, reg, cur_rx);
+ ok &= _write_9862 (codec, REG_RX_PWR_DN, cur_pwr_dn);
+ return ok;
+}
+
+bool
+usrp_basic::set_dc_offset_cl_enable(int bits, int mask)
+{
+ return _write_fpga_reg(FR_DC_OFFSET_CL_EN,
+ (d_fpga_shadows[FR_DC_OFFSET_CL_EN] & ~mask) | (bits & mask));
+}
+
+// ----------------------------------------------------------------
+
+bool
+usrp_basic::_write_fpga_reg (int regno, int value)
+{
+ if (d_verbose){
+ fprintf (stdout, "_write_fpga_reg(%3d, 0x%08x)\n", regno, value);
+ fflush (stdout);
+ }
+
+ if (regno >= 0 && regno < MAX_REGS)
+ d_fpga_shadows[regno] = value;
+
+ return usrp_write_fpga_reg (d_udh, regno, value);
+}
+
+bool
+usrp_basic::_write_fpga_reg_masked (int regno, int value, int mask)
+{
+ //Only use this for registers who actually use a mask in the verilog firmware, like FR_RX_MASTER_SLAVE
+ //value is a 16 bits value and mask is a 16 bits mask
+ if (d_verbose){
+ fprintf (stdout, "_write_fpga_reg_masked(%3d, 0x%04x,0x%04x)\n", regno, value, mask);
+ fflush (stdout);
+ }
+
+ if (regno >= 0 && regno < MAX_REGS)
+ d_fpga_shadows[regno] = value;
+
+ return usrp_write_fpga_reg (d_udh, regno, (value & 0xffff) | ((mask & 0xffff)<<16));
+}
+
+
+bool
+usrp_basic::_read_fpga_reg (int regno, int *value)
+{
+ return usrp_read_fpga_reg (d_udh, regno, value);
+}
+
+int
+usrp_basic::_read_fpga_reg (int regno)
+{
+ int value;
+ if (!_read_fpga_reg (regno, &value))
+ return READ_FAILED;
+ return value;
+}
+
+bool
+usrp_basic::_write_9862 (int which_codec, int regno, unsigned char value)
+{
+ if (0 && d_verbose){
+ // FIXME really want to enable logging in usrp_prims:usrp_9862_write
+ fprintf(stdout, "_write_9862(codec = %d, regno = %2d, val = 0x%02x)\n", which_codec, regno, value);
+ fflush(stdout);
+ }
+
+ return usrp_9862_write (d_udh, which_codec, regno, value);
+}
+
+
+bool
+usrp_basic::_read_9862 (int which_codec, int regno, unsigned char *value) const
+{
+ return usrp_9862_read (d_udh, which_codec, regno, value);
+}
+
+int
+usrp_basic::_read_9862 (int which_codec, int regno) const
+{
+ unsigned char value;
+ if (!_read_9862 (which_codec, regno, &value))
+ return READ_FAILED;
+ return value;
+}
+
+bool
+usrp_basic::_write_spi (int optional_header, int enables, int format, std::string buf)
+{
+ return usrp_spi_write (d_udh, optional_header, enables, format,
+ buf.data(), buf.size());
+}
+
+std::string
+usrp_basic::_read_spi (int optional_header, int enables, int format, int len)
+{
+ if (len <= 0)
+ return "";
+
+ char buf[len];
+
+ if (!usrp_spi_read (d_udh, optional_header, enables, format, buf, len))
+ return "";
+
+ return std::string (buf, len);
+}
+
+
+bool
+usrp_basic::_set_led (int which_led, bool on)
+{
+ return usrp_set_led (d_udh, which_led, on);
+}
+
+bool
+usrp_basic::write_atr_tx_delay(int value)
+{
+ return _write_fpga_reg(FR_ATR_TX_DELAY, value);
+}
+
+bool
+usrp_basic::write_atr_rx_delay(int value)
+{
+ return _write_fpga_reg(FR_ATR_RX_DELAY, value);
+}
+
+/*
+ * ----------------------------------------------------------------
+ * Routines to access and control daughterboard specific i/o
+ * ----------------------------------------------------------------
+ */
+static int
+slot_id_to_oe_reg (int slot_id)
+{
+ static int reg[4] = { FR_OE_0, FR_OE_1, FR_OE_2, FR_OE_3 };
+ assert (0 <= slot_id && slot_id < 4);
+ return reg[slot_id];
+}
+
+static int
+slot_id_to_io_reg (int slot_id)
+{
+ static int reg[4] = { FR_IO_0, FR_IO_1, FR_IO_2, FR_IO_3 };
+ assert (0 <= slot_id && slot_id < 4);
+ return reg[slot_id];
+}
+
+static int
+slot_id_to_refclk_reg(int slot_id)
+{
+ static int reg[4] = { FR_TX_A_REFCLK, FR_RX_A_REFCLK, FR_TX_B_REFCLK, FR_RX_B_REFCLK };
+ assert (0 <= slot_id && slot_id < 4);
+ return reg[slot_id];
+}
+
+static int
+slot_id_to_atr_mask_reg(int slot_id)
+{
+ static int reg[4] = { FR_ATR_MASK_0, FR_ATR_MASK_1, FR_ATR_MASK_2, FR_ATR_MASK_3 };
+ assert (0 <= slot_id && slot_id < 4);
+ return reg[slot_id];
+}
+
+static int
+slot_id_to_atr_txval_reg(int slot_id)
+{
+ static int reg[4] = { FR_ATR_TXVAL_0, FR_ATR_TXVAL_1, FR_ATR_TXVAL_2, FR_ATR_TXVAL_3 };
+ assert (0 <= slot_id && slot_id < 4);
+ return reg[slot_id];
+}
+
+static int
+slot_id_to_atr_rxval_reg(int slot_id)
+{
+ static int reg[4] = { FR_ATR_RXVAL_0, FR_ATR_RXVAL_1, FR_ATR_RXVAL_2, FR_ATR_RXVAL_3 };
+ assert (0 <= slot_id && slot_id < 4);
+ return reg[slot_id];
+}
+
+static int
+to_slot(txrx_t txrx, int which_side)
+{
+ // TX_A = 0
+ // RX_A = 1
+ // TX_B = 2
+ // RX_B = 3
+ return ((which_side & 0x1) << 1) | ((txrx & 0x1) == C_RX);
+}
+
+bool
+usrp_basic::common_set_pga(txrx_t txrx, int which_amp, double gain)
+{
+ if (which_amp < 0 || which_amp > 3)
+ return false;
+
+ gain = std::min(common_pga_max(txrx),
+ std::max(common_pga_min(txrx), gain));
+
+ int codec = which_amp >> 1;
+ int int_gain = (int) rint((gain - common_pga_min(txrx)) / common_pga_db_per_step(txrx));
+
+ if (txrx == C_TX){ // 0 and 1 are same, as are 2 and 3
+ return _write_9862(codec, REG_TX_PGA, int_gain);
+ }
+ else {
+ int reg = (which_amp & 1) == 0 ? REG_RX_A : REG_RX_B;
+
+ // read current value to get input buffer bypass flag.
+ unsigned char cur_rx;
+ if (!_read_9862(codec, reg, &cur_rx))
+ return false;
+
+ cur_rx = (cur_rx & RX_X_BYPASS_INPUT_BUFFER) | (int_gain & 0x7f);
+ return _write_9862(codec, reg, cur_rx);
+ }
+}
+
+double
+usrp_basic::common_pga(txrx_t txrx, int which_amp) const
+{
+ if (which_amp < 0 || which_amp > 3)
+ return READ_FAILED;
+
+ if (txrx == C_TX){
+ int codec = which_amp >> 1;
+ unsigned char v;
+ bool ok = _read_9862 (codec, REG_TX_PGA, &v);
+ if (!ok)
+ return READ_FAILED;
+
+ return (pga_db_per_step() * v) + pga_min();
+ }
+ else {
+ int codec = which_amp >> 1;
+ int reg = (which_amp & 1) == 0 ? REG_RX_A : REG_RX_B;
+ unsigned char v;
+ bool ok = _read_9862 (codec, reg, &v);
+ if (!ok)
+ return READ_FAILED;
+
+ return (pga_db_per_step() * (v & 0x1f)) + pga_min();
+ }
+}
+
+double
+usrp_basic::common_pga_min(txrx_t txrx) const
+{
+ if (txrx == C_TX)
+ return -20.0;
+ else
+ return 0.0;
+}
+
+double
+usrp_basic::common_pga_max(txrx_t txrx) const
+{
+ if (txrx == C_TX)
+ return 0.0;
+ else
+ return 20.0;
+}
+
+double
+usrp_basic::common_pga_db_per_step(txrx_t txrx) const
+{
+ if (txrx == C_TX)
+ return 20.0 / 255;
+ else
+ return 20.0 / 20;
+}
+
+bool
+usrp_basic::_common_write_oe(txrx_t txrx, int which_side, int value, int mask)
+{
+ if (! (0 <= which_side && which_side <= 1))
+ return false;
+
+ return _write_fpga_reg(slot_id_to_oe_reg(to_slot(txrx, which_side)),
+ (mask << 16) | (value & 0xffff));
+}
+
+bool
+usrp_basic::common_write_io(txrx_t txrx, int which_side, int value, int mask)
+{
+ if (! (0 <= which_side && which_side <= 1))
+ return false;
+
+ return _write_fpga_reg(slot_id_to_io_reg(to_slot(txrx, which_side)),
+ (mask << 16) | (value & 0xffff));
+}
+
+bool
+usrp_basic::common_read_io(txrx_t txrx, int which_side, int *value)
+{
+ if (! (0 <= which_side && which_side <= 1))
+ return false;
+
+ int t;
+ int reg = which_side + 1; // FIXME, *very* magic number (fix in serial_io.v)
+ bool ok = _read_fpga_reg(reg, &t);
+ if (!ok)
+ return false;
+
+ if (txrx == C_TX){
+ *value = t & 0xffff; // FIXME, more magic
+ return true;
+ }
+ else {
+ *value = (t >> 16) & 0xffff; // FIXME, more magic
+ return true;
+ }
+}
+
+int
+usrp_basic::common_read_io(txrx_t txrx, int which_side)
+{
+ int value;
+ if (!common_read_io(txrx, which_side, &value))
+ return READ_FAILED;
+ return value;
+}
+
+bool
+usrp_basic::common_write_refclk(txrx_t txrx, int which_side, int value)
+{
+ if (! (0 <= which_side && which_side <= 1))
+ return false;
+
+ return _write_fpga_reg(slot_id_to_refclk_reg(to_slot(txrx, which_side)),
+ value);
+}
+
+bool
+usrp_basic::common_write_atr_mask(txrx_t txrx, int which_side, int value)
+{
+ if (! (0 <= which_side && which_side <= 1))
+ return false;
+
+ return _write_fpga_reg(slot_id_to_atr_mask_reg(to_slot(txrx, which_side)),
+ value);
+}
+
+bool
+usrp_basic::common_write_atr_txval(txrx_t txrx, int which_side, int value)
+{
+ if (! (0 <= which_side && which_side <= 1))
+ return false;
+
+ return _write_fpga_reg(slot_id_to_atr_txval_reg(to_slot(txrx, which_side)),
+ value);
+}
+
+bool
+usrp_basic::common_write_atr_rxval(txrx_t txrx, int which_side, int value)
+{
+ if (! (0 <= which_side && which_side <= 1))
+ return false;
+
+ return _write_fpga_reg(slot_id_to_atr_rxval_reg(to_slot(txrx, which_side)),
+ value);
+}
+
+bool
+usrp_basic::common_write_aux_dac(txrx_t txrx, int which_side, int which_dac, int value)
+{
+ return _write_aux_dac(to_slot(txrx, which_side), which_dac, value);
+}
+
+bool
+usrp_basic::common_read_aux_adc(txrx_t txrx, int which_side, int which_adc, int *value)
+{
+ return _read_aux_adc(to_slot(txrx, which_side), which_adc, value);
+}
+
+int
+usrp_basic::common_read_aux_adc(txrx_t txrx, int which_side, int which_adc)
+{
+ return _read_aux_adc(to_slot(txrx, which_side), which_adc);
+}
+
+
+////////////////////////////////////////////////////////////////
+//
+// usrp_basic_rx
+//
+////////////////////////////////////////////////////////////////
+
+static unsigned char rx_init_regs[] = {
+ REG_RX_PWR_DN, 0,
+ REG_RX_A, 0, // minimum gain = 0x00 (max gain = 0x14)
+ REG_RX_B, 0, // minimum gain = 0x00 (max gain = 0x14)
+ REG_RX_MISC, (RX_MISC_HS_DUTY_CYCLE | RX_MISC_CLK_DUTY),
+ REG_RX_IF, (RX_IF_USE_CLKOUT1
+ | RX_IF_2S_COMP),
+ REG_RX_DIGITAL, (RX_DIGITAL_2_CHAN)
+};
+
+
+usrp_basic_rx::usrp_basic_rx (int which_board, int fusb_block_size, int fusb_nblocks,
+ const std::string fpga_filename,
+ const std::string firmware_filename
+ )
+ : usrp_basic (which_board, open_rx_interface, fpga_filename, firmware_filename),
+ d_devhandle (0), d_ephandle (0),
+ d_bytes_seen (0), d_first_read (true),
+ d_rx_enable (false)
+{
+ // initialize rx specific registers
+
+ if (!usrp_9862_write_many_all (d_udh, rx_init_regs, sizeof (rx_init_regs))){
+ fprintf (stderr, "usrp_basic_rx: failed to init AD9862 RX regs\n");
+ throw std::runtime_error ("usrp_basic_rx/init_9862");
+ }
+
+ if (0){
+ // FIXME power down 2nd codec rx path
+ usrp_9862_write (d_udh, 1, REG_RX_PWR_DN, 0x1); // power down everything
+ }
+
+ // Reset the rx path and leave it disabled.
+ set_rx_enable (false);
+ usrp_set_fpga_rx_reset (d_udh, true);
+ usrp_set_fpga_rx_reset (d_udh, false);
+
+ set_fpga_rx_sample_rate_divisor (2); // usually correct
+
+ set_dc_offset_cl_enable(0xf, 0xf); // enable DC offset removal control loops
+
+ probe_rx_slots (false);
+
+ //d_db[0] = instantiate_dbs(d_dbid[0], this, 0);
+ //d_db[1] = instantiate_dbs(d_dbid[1], this, 1);
+
+ // check fusb buffering parameters
+
+ if (fusb_block_size < 0 || fusb_block_size > FUSB_BLOCK_SIZE)
+ throw std::out_of_range ("usrp_basic_rx: invalid fusb_block_size");
+
+ if (fusb_nblocks < 0)
+ throw std::out_of_range ("usrp_basic_rx: invalid fusb_nblocks");
+
+ if (fusb_block_size == 0)
+ fusb_block_size = fusb_sysconfig::default_block_size();
+
+ if (fusb_nblocks == 0)
+ fusb_nblocks = std::max (1, FUSB_BUFFER_SIZE / fusb_block_size);
+
+ d_devhandle = fusb_sysconfig::make_devhandle (d_udh, d_ctx);
+ d_ephandle = d_devhandle->make_ephandle (USRP_RX_ENDPOINT, true,
+ fusb_block_size, fusb_nblocks);
+
+ write_atr_mask(0, 0); // zero Rx A Auto Transmit/Receive regs
+ write_atr_txval(0, 0);
+ write_atr_rxval(0, 0);
+ write_atr_mask(1, 0); // zero Rx B Auto Transmit/Receive regs
+ write_atr_txval(1, 0);
+ write_atr_rxval(1, 0);
+}
+
+static unsigned char rx_fini_regs[] = {
+ REG_RX_PWR_DN, 0x1 // power down everything
+};
+
+usrp_basic_rx::~usrp_basic_rx ()
+{
+ if (!set_rx_enable (false)){
+ fprintf (stderr, "usrp_basic_rx: set_fpga_rx_enable failed\n");
+ }
+
+ d_ephandle->stop ();
+ delete d_ephandle;
+ delete d_devhandle;
+
+ if (!usrp_9862_write_many_all (d_udh, rx_fini_regs, sizeof (rx_fini_regs))){
+ fprintf (stderr, "usrp_basic_rx: failed to fini AD9862 RX regs\n");
+ }
+
+ shutdown_daughterboards();
+}
+
+
+bool
+usrp_basic_rx::start ()
+{
+ if (!usrp_basic::start ()) // invoke parent's method
+ return false;
+
+ // fire off reads before asserting rx_enable
+
+ if (!d_ephandle->start ()){
+ fprintf (stderr, "usrp_basic_rx: failed to start end point streaming");
+ return false;
+ }
+
+ if (!set_rx_enable (true)){
+ fprintf (stderr, "usrp_basic_rx: set_rx_enable failed\n");
+ return false;
+ }
+
+ return true;
+}
+
+bool
+usrp_basic_rx::stop ()
+{
+ bool ok = usrp_basic::stop();
+
+ if (!set_rx_enable(false)){
+ fprintf (stderr, "usrp_basic_rx: set_rx_enable(false) failed\n");
+ ok = false;
+ }
+
+ if (!d_ephandle->stop()){
+ fprintf (stderr, "usrp_basic_rx: failed to stop end point streaming");
+ ok = false;
+ }
+
+ return ok;
+}
+
+usrp_basic_rx *
+usrp_basic_rx::make (int which_board, int fusb_block_size, int fusb_nblocks,
+ const std::string fpga_filename,
+ const std::string firmware_filename)
+{
+ usrp_basic_rx *u = 0;
+
+ try {
+ u = new usrp_basic_rx (which_board, fusb_block_size, fusb_nblocks,
+ fpga_filename, firmware_filename);
+ return u;
+ }
+ catch (...){
+ delete u;
+ return 0;
+ }
+
+ return u;
+}
+
+bool
+usrp_basic_rx::set_fpga_rx_sample_rate_divisor (unsigned int div)
+{
+ return _write_fpga_reg (FR_RX_SAMPLE_RATE_DIV, div - 1);
+}
+
+
+/*
+ * \brief read data from the D/A's via the FPGA.
+ * \p len must be a multiple of 512 bytes.
+ *
+ * \returns the number of bytes read, or -1 on error.
+ *
+ * If overrun is non-NULL it will be set true iff an RX overrun is detected.
+ */
+int
+usrp_basic_rx::read (void *buf, int len, bool *overrun)
+{
+ int r;
+
+ if (overrun)
+ *overrun = false;
+
+ if (len < 0 || (len % 512) != 0){
+ fprintf (stderr, "usrp_basic_rx::read: invalid length = %d\n", len);
+ return -1;
+ }
+
+ r = d_ephandle->read (buf, len);
+ if (r > 0)
+ d_bytes_seen += r;
+
+ /*
+ * In many cases, the FPGA reports an rx overrun right after we
+ * enable the Rx path. If this is our first read, check for the
+ * overrun to clear the condition, then ignore the result.
+ */
+ if (0 && d_first_read){ // FIXME
+ d_first_read = false;
+ bool bogus_overrun;
+ usrp_check_rx_overrun (d_udh, &bogus_overrun);
+ }
+
+ if (overrun != 0 && d_bytes_seen >= d_bytes_per_poll){
+ d_bytes_seen = 0;
+ if (!usrp_check_rx_overrun (d_udh, overrun)){
+ fprintf (stderr, "usrp_basic_rx: usrp_check_rx_overrun failed\n");
+ }
+ }
+
+ return r;
+}
+
+bool
+usrp_basic_rx::set_rx_enable (bool on)
+{
+ d_rx_enable = on;
+ return usrp_set_fpga_rx_enable (d_udh, on);
+}
+
+// conditional disable, return prev state
+bool
+usrp_basic_rx::disable_rx ()
+{
+ bool enabled = rx_enable ();
+ if (enabled)
+ set_rx_enable (false);
+ return enabled;
+}
+
+// conditional set
+void
+usrp_basic_rx::restore_rx (bool on)
+{
+ if (on != rx_enable ())
+ set_rx_enable (on);
+}
+
+void
+usrp_basic_rx::probe_rx_slots (bool verbose)
+{
+ struct usrp_dboard_eeprom eeprom;
+ static int slot_id_map[2] = { SLOT_RX_A, SLOT_RX_B };
+ static const char *slot_name[2] = { "RX d'board A", "RX d'board B" };
+
+ for (int i = 0; i < 2; i++){
+ int slot_id = slot_id_map [i];
+ const char *msg = 0;
+ usrp_dbeeprom_status_t s = usrp_read_dboard_eeprom (d_udh, slot_id, &eeprom);
+
+ switch (s){
+ case UDBE_OK:
+ d_dbid[i] = eeprom.id;
+ msg = usrp_dbid_to_string (eeprom.id).c_str ();
+ set_adc_offset (2*i+0, eeprom.offset[0]);
+ set_adc_offset (2*i+1, eeprom.offset[1]);
+ _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | eeprom.oe);
+ _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
+ break;
+
+ case UDBE_NO_EEPROM:
+ d_dbid[i] = -1;
+ msg = "<none>";
+ _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
+ _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
+ break;
+
+ case UDBE_INVALID_EEPROM:
+ d_dbid[i] = -2;
+ msg = "Invalid EEPROM contents";
+ _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
+ _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
+ break;
+
+ case UDBE_BAD_SLOT:
+ default:
+ assert (0);
+ }
+
+ if (verbose){
+ fflush (stdout);
+ fprintf (stderr, "%s: %s\n", slot_name[i], msg);
+ }
+ }
+}
+
+bool
+usrp_basic_rx::set_pga (int which_amp, double gain)
+{
+ return common_set_pga(C_RX, which_amp, gain);
+}
+
+double
+usrp_basic_rx::pga(int which_amp) const
+{
+ return common_pga(C_RX, which_amp);
+}
+
+double
+usrp_basic_rx::pga_min() const
+{
+ return common_pga_min(C_RX);
+}
+
+double
+usrp_basic_rx::pga_max() const
+{
+ return common_pga_max(C_RX);
+}
+
+double
+usrp_basic_rx::pga_db_per_step() const
+{
+ return common_pga_db_per_step(C_RX);
+}
+
+bool
+usrp_basic_rx::_write_oe (int which_side, int value, int mask)
+{
+ return _common_write_oe(C_RX, which_side, value, mask);
+}
+
+bool
+usrp_basic_rx::write_io (int which_side, int value, int mask)
+{
+ return common_write_io(C_RX, which_side, value, mask);
+}
+
+bool
+usrp_basic_rx::read_io (int which_side, int *value)
+{
+ return common_read_io(C_RX, which_side, value);
+}
+
+int
+usrp_basic_rx::read_io (int which_side)
+{
+ return common_read_io(C_RX, which_side);
+}
+
+bool
+usrp_basic_rx::write_refclk(int which_side, int value)
+{
+ return common_write_refclk(C_RX, which_side, value);
+}
+
+bool
+usrp_basic_rx::write_atr_mask(int which_side, int value)
+{
+ return common_write_atr_mask(C_RX, which_side, value);
+}
+
+bool
+usrp_basic_rx::write_atr_txval(int which_side, int value)
+{
+ return common_write_atr_txval(C_RX, which_side, value);
+}
+
+bool
+usrp_basic_rx::write_atr_rxval(int which_side, int value)
+{
+ return common_write_atr_rxval(C_RX, which_side, value);
+}
+
+bool
+usrp_basic_rx::write_aux_dac (int which_side, int which_dac, int value)
+{
+ return common_write_aux_dac(C_RX, which_side, which_dac, value);
+}
+
+bool
+usrp_basic_rx::read_aux_adc (int which_side, int which_adc, int *value)
+{
+ return common_read_aux_adc(C_RX, which_side, which_adc, value);
+}
+
+int
+usrp_basic_rx::read_aux_adc (int which_side, int which_adc)
+{
+ return common_read_aux_adc(C_RX, which_side, which_adc);
+}
+
+int
+usrp_basic_rx::block_size () const { return d_ephandle->block_size(); }
+
+////////////////////////////////////////////////////////////////
+//
+// usrp_basic_tx
+//
+////////////////////////////////////////////////////////////////
+
+
+//
+// DAC input rate 64 MHz interleaved for a total input rate of 128 MHz
+// DAC input is latched on rising edge of CLKOUT2
+// NCO is disabled
+// interpolate 2x
+// coarse modulator disabled
+//
+
+static unsigned char tx_init_regs[] = {
+ REG_TX_PWR_DN, 0,
+ REG_TX_A_OFFSET_LO, 0,
+ REG_TX_A_OFFSET_HI, 0,
+ REG_TX_B_OFFSET_LO, 0,
+ REG_TX_B_OFFSET_HI, 0,
+ REG_TX_A_GAIN, (TX_X_GAIN_COARSE_FULL | 0),
+ REG_TX_B_GAIN, (TX_X_GAIN_COARSE_FULL | 0),
+ REG_TX_PGA, 0xff, // maximum gain (0 dB)
+ REG_TX_MISC, 0,
+ REG_TX_IF, (TX_IF_USE_CLKOUT1
+ | TX_IF_I_FIRST
+ | TX_IF_INV_TX_SYNC
+ | TX_IF_2S_COMP
+ | TX_IF_INTERLEAVED),
+ REG_TX_DIGITAL, (TX_DIGITAL_2_DATA_PATHS
+ | TX_DIGITAL_INTERPOLATE_4X),
+ REG_TX_MODULATOR, (TX_MODULATOR_DISABLE_NCO
+ | TX_MODULATOR_COARSE_MODULATION_NONE),
+ REG_TX_NCO_FTW_7_0, 0,
+ REG_TX_NCO_FTW_15_8, 0,
+ REG_TX_NCO_FTW_23_16, 0
+};
+
+usrp_basic_tx::usrp_basic_tx (int which_board, int fusb_block_size, int fusb_nblocks,
+ const std::string fpga_filename,
+ const std::string firmware_filename)
+ : usrp_basic (which_board, open_tx_interface, fpga_filename, firmware_filename),
+ d_devhandle (0), d_ephandle (0),
+ d_bytes_seen (0), d_first_write (true),
+ d_tx_enable (false)
+{
+ if (!usrp_9862_write_many_all (d_udh, tx_init_regs, sizeof (tx_init_regs))){
+ fprintf (stderr, "usrp_basic_tx: failed to init AD9862 TX regs\n");
+ throw std::runtime_error ("usrp_basic_tx/init_9862");
+ }
+
+ if (0){
+ // FIXME power down 2nd codec tx path
+ usrp_9862_write (d_udh, 1, REG_TX_PWR_DN,
+ (TX_PWR_DN_TX_DIGITAL
+ | TX_PWR_DN_TX_ANALOG_BOTH));
+ }
+
+ // Reset the tx path and leave it disabled.
+ set_tx_enable (false);
+ usrp_set_fpga_tx_reset (d_udh, true);
+ usrp_set_fpga_tx_reset (d_udh, false);
+
+ set_fpga_tx_sample_rate_divisor (4); // we're using interp x4
+
+ probe_tx_slots (false);
+
+ //d_db[0] = instantiate_dbs(d_dbid[0], this, 0);
+ //d_db[1] = instantiate_dbs(d_dbid[1], this, 1);
+
+ // check fusb buffering parameters
+
+ if (fusb_block_size < 0 || fusb_block_size > FUSB_BLOCK_SIZE)
+ throw std::out_of_range ("usrp_basic_rx: invalid fusb_block_size");
+
+ if (fusb_nblocks < 0)
+ throw std::out_of_range ("usrp_basic_rx: invalid fusb_nblocks");
+
+ if (fusb_block_size == 0)
+ fusb_block_size = FUSB_BLOCK_SIZE;
+
+ if (fusb_nblocks == 0)
+ fusb_nblocks = std::max (1, FUSB_BUFFER_SIZE / fusb_block_size);
+
+ d_devhandle = fusb_sysconfig::make_devhandle (d_udh, d_ctx);
+ d_ephandle = d_devhandle->make_ephandle (USRP_TX_ENDPOINT, false,
+ fusb_block_size, fusb_nblocks);
+
+ write_atr_mask(0, 0); // zero Tx A Auto Transmit/Receive regs
+ write_atr_txval(0, 0);
+ write_atr_rxval(0, 0);
+ write_atr_mask(1, 0); // zero Tx B Auto Transmit/Receive regs
+ write_atr_txval(1, 0);
+ write_atr_rxval(1, 0);
+}
+
+
+static unsigned char tx_fini_regs[] = {
+ REG_TX_PWR_DN, (TX_PWR_DN_TX_DIGITAL
+ | TX_PWR_DN_TX_ANALOG_BOTH),
+ REG_TX_MODULATOR, (TX_MODULATOR_DISABLE_NCO
+ | TX_MODULATOR_COARSE_MODULATION_NONE)
+};
+
+usrp_basic_tx::~usrp_basic_tx ()
+{
+ d_ephandle->stop ();
+ delete d_ephandle;
+ delete d_devhandle;
+
+ if (!usrp_9862_write_many_all (d_udh, tx_fini_regs, sizeof (tx_fini_regs))){
+ fprintf (stderr, "usrp_basic_tx: failed to fini AD9862 TX regs\n");
+ }
+
+ shutdown_daughterboards();
+}
+
+bool
+usrp_basic_tx::start ()
+{
+ if (!usrp_basic::start ())
+ return false;
+
+ if (!set_tx_enable (true)){
+ fprintf (stderr, "usrp_basic_tx: set_tx_enable failed\n");
+ return false;
+ }
+
+ if (!d_ephandle->start ()){
+ fprintf (stderr, "usrp_basic_tx: failed to start end point streaming");
+ return false;
+ }
+
+ return true;
+}
+
+bool
+usrp_basic_tx::stop ()
+{
+ bool ok = usrp_basic::stop ();
+
+ if (!d_ephandle->stop ()){
+ fprintf (stderr, "usrp_basic_tx: failed to stop end point streaming");
+ ok = false;
+ }
+
+ if (!set_tx_enable (false)){
+ fprintf (stderr, "usrp_basic_tx: set_tx_enable(false) failed\n");
+ ok = false;
+ }
+
+ return ok;
+}
+
+usrp_basic_tx *
+usrp_basic_tx::make (int which_board, int fusb_block_size, int fusb_nblocks,
+ const std::string fpga_filename,
+ const std::string firmware_filename)
+{
+ usrp_basic_tx *u = 0;
+
+ try {
+ u = new usrp_basic_tx (which_board, fusb_block_size, fusb_nblocks,
+ fpga_filename, firmware_filename);
+ return u;
+ }
+ catch (...){
+ delete u;
+ return 0;
+ }
+
+ return u;
+}
+
+bool
+usrp_basic_tx::set_fpga_tx_sample_rate_divisor (unsigned int div)
+{
+ return _write_fpga_reg (FR_TX_SAMPLE_RATE_DIV, div - 1);
+}
+
+/*!
+ * \brief Write data to the A/D's via the FPGA.
+ *
+ * \p len must be a multiple of 512 bytes.
+ * \returns number of bytes written or -1 on error.
+ *
+ * if \p underrun is non-NULL, it will be set to true iff
+ * a transmit underrun condition is detected.
+ */
+int
+usrp_basic_tx::write (const void *buf, int len, bool *underrun)
+{
+ int r;
+
+ if (underrun)
+ *underrun = false;
+
+ if (len < 0 || (len % 512) != 0){
+ fprintf (stderr, "usrp_basic_tx::write: invalid length = %d\n", len);
+ return -1;
+ }
+
+ r = d_ephandle->write (buf, len);
+ if (r > 0)
+ d_bytes_seen += r;
+
+ /*
+ * In many cases, the FPGA reports an tx underrun right after we
+ * enable the Tx path. If this is our first write, check for the
+ * underrun to clear the condition, then ignore the result.
+ */
+ if (d_first_write && d_bytes_seen >= 4 * FUSB_BLOCK_SIZE){
+ d_first_write = false;
+ bool bogus_underrun;
+ usrp_check_tx_underrun (d_udh, &bogus_underrun);
+ }
+
+ if (underrun != 0 && d_bytes_seen >= d_bytes_per_poll){
+ d_bytes_seen = 0;
+ if (!usrp_check_tx_underrun (d_udh, underrun)){
+ fprintf (stderr, "usrp_basic_tx: usrp_check_tx_underrun failed\n");
+ }
+ }
+
+ return r;
+}
+
+void
+usrp_basic_tx::wait_for_completion ()
+{
+ d_ephandle->wait_for_completion ();
+}
+
+bool
+usrp_basic_tx::set_tx_enable (bool on)
+{
+ d_tx_enable = on;
+ // fprintf (stderr, "set_tx_enable %d\n", on);
+ return usrp_set_fpga_tx_enable (d_udh, on);
+}
+
+// conditional disable, return prev state
+bool
+usrp_basic_tx::disable_tx ()
+{
+ bool enabled = tx_enable ();
+ if (enabled)
+ set_tx_enable (false);
+ return enabled;
+}
+
+// conditional set
+void
+usrp_basic_tx::restore_tx (bool on)
+{
+ if (on != tx_enable ())
+ set_tx_enable (on);
+}
+
+void
+usrp_basic_tx::probe_tx_slots (bool verbose)
+{
+ struct usrp_dboard_eeprom eeprom;
+ static int slot_id_map[2] = { SLOT_TX_A, SLOT_TX_B };
+ static const char *slot_name[2] = { "TX d'board A", "TX d'board B" };
+
+ for (int i = 0; i < 2; i++){
+ int slot_id = slot_id_map [i];
+ const char *msg = 0;
+ usrp_dbeeprom_status_t s = usrp_read_dboard_eeprom (d_udh, slot_id, &eeprom);
+
+ switch (s){
+ case UDBE_OK:
+ d_dbid[i] = eeprom.id;
+ msg = usrp_dbid_to_string (eeprom.id).c_str ();
+ // FIXME, figure out interpretation of dc offset for TX d'boards
+ // offset = (eeprom.offset[1] << 16) | (eeprom.offset[0] & 0xffff);
+ _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | eeprom.oe);
+ _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
+ break;
+
+ case UDBE_NO_EEPROM:
+ d_dbid[i] = -1;
+ msg = "<none>";
+ _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
+ _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
+ break;
+
+ case UDBE_INVALID_EEPROM:
+ d_dbid[i] = -2;
+ msg = "Invalid EEPROM contents";
+ _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
+ _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
+ break;
+
+ case UDBE_BAD_SLOT:
+ default:
+ assert (0);
+ }
+
+ if (verbose){
+ fflush (stdout);
+ fprintf (stderr, "%s: %s\n", slot_name[i], msg);
+ }
+ }
+}
+
+bool
+usrp_basic_tx::set_pga (int which_amp, double gain)
+{
+ return common_set_pga(C_TX, which_amp, gain);
+}
+
+double
+usrp_basic_tx::pga (int which_amp) const
+{
+ return common_pga(C_TX, which_amp);
+}
+
+double
+usrp_basic_tx::pga_min() const
+{
+ return common_pga_min(C_TX);
+}
+
+double
+usrp_basic_tx::pga_max() const
+{
+ return common_pga_max(C_TX);
+}
+
+double
+usrp_basic_tx::pga_db_per_step() const
+{
+ return common_pga_db_per_step(C_TX);
+}
+
+bool
+usrp_basic_tx::_write_oe (int which_side, int value, int mask)
+{
+ return _common_write_oe(C_TX, which_side, value, mask);
+}
+
+bool
+usrp_basic_tx::write_io (int which_side, int value, int mask)
+{
+ return common_write_io(C_TX, which_side, value, mask);
+}
+
+bool
+usrp_basic_tx::read_io (int which_side, int *value)
+{
+ return common_read_io(C_TX, which_side, value);
+}
+
+int
+usrp_basic_tx::read_io (int which_side)
+{
+ return common_read_io(C_TX, which_side);
+}
+
+bool
+usrp_basic_tx::write_refclk(int which_side, int value)
+{
+ return common_write_refclk(C_TX, which_side, value);
+}
+
+bool
+usrp_basic_tx::write_atr_mask(int which_side, int value)
+{
+ return common_write_atr_mask(C_TX, which_side, value);
+}
+
+bool
+usrp_basic_tx::write_atr_txval(int which_side, int value)
+{
+ return common_write_atr_txval(C_TX, which_side, value);
+}
+
+bool
+usrp_basic_tx::write_atr_rxval(int which_side, int value)
+{
+ return common_write_atr_rxval(C_TX, which_side, value);
+}
+
+bool
+usrp_basic_tx::write_aux_dac (int which_side, int which_dac, int value)
+{
+ return common_write_aux_dac(C_TX, which_side, which_dac, value);
+}
+
+bool
+usrp_basic_tx::read_aux_adc (int which_side, int which_adc, int *value)
+{
+ return common_read_aux_adc(C_TX, which_side, which_adc, value);
+}
+
+int
+usrp_basic_tx::read_aux_adc (int which_side, int which_adc)
+{
+ return common_read_aux_adc(C_TX, which_side, which_adc);
+}
+
+int
+usrp_basic_tx::block_size () const { return d_ephandle->block_size(); }
+
--- /dev/null
+/* -*- c++ -*- */
+/*
+ * Copyright 2003,2004,2008,2009 Free Software Foundation, Inc.
+ *
+ * This file is part of GNU Radio
+ *
+ * GNU Radio is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3, or (at your option)
+ * any later version.
+ *
+ * GNU Radio is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with GNU Radio; see the file COPYING. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <usrp/usrp_basic.h>
+#include "usrp/usrp_prims.h"
+#include "usrp_interfaces.h"
+#include "fpga_regs_common.h"
+#include "fpga_regs_standard.h"
+#include "fusb.h"
+#include "db_boards.h"
+#include <usb.h>
+#include <stdexcept>
+#include <assert.h>
+#include <math.h>
+#include <ad9862.h>
+#include <string.h>
+#include <cstdio>
+
+
+using namespace ad9862;
+
+#define NELEM(x) (sizeof (x) / sizeof (x[0]))
+
+// These set the buffer size used for each end point using the fast
+// usb interface. The kernel ends up locking down this much memory.
+
+static const int FUSB_BUFFER_SIZE = fusb_sysconfig::default_buffer_size();
+static const int FUSB_BLOCK_SIZE = fusb_sysconfig::max_block_size();
+static const int FUSB_NBLOCKS = FUSB_BUFFER_SIZE / FUSB_BLOCK_SIZE;
+
+
+static const double POLLING_INTERVAL = 0.1; // seconds
+
+
+//////////////////////////////////////////////////////////////////
+//
+// usrp_basic
+//
+////////////////////////////////////////////////////////////////
+
+
+// Given:
+// CLKIN = 64 MHz
+// CLKSEL pin = high
+//
+// These settings give us:
+// CLKOUT1 = CLKIN = 64 MHz
+// CLKOUT2 = CLKIN = 64 MHz
+// ADC is clocked at 64 MHz
+// DAC is clocked at 128 MHz
+
+static unsigned char common_regs[] = {
+ REG_GENERAL, 0,
+ REG_DLL, (DLL_DISABLE_INTERNAL_XTAL_OSC
+ | DLL_MULT_2X
+ | DLL_FAST),
+ REG_CLKOUT, CLKOUT2_EQ_DLL_OVER_2,
+ REG_AUX_ADC_CLK, AUX_ADC_CLK_CLK_OVER_4
+};
+
+
+usrp_basic::usrp_basic (int which_board,
+ struct usb_dev_handle *
+ open_interface (struct usb_device *dev),
+ const std::string fpga_filename,
+ const std::string firmware_filename)
+ : d_udh (0),
+ d_usb_data_rate (16000000), // SWAG, see below
+ d_bytes_per_poll ((int) (POLLING_INTERVAL * d_usb_data_rate)),
+ d_verbose (false), d_fpga_master_clock_freq(64000000), d_db(2)
+{
+ /*
+ * SWAG: Scientific Wild Ass Guess.
+ *
+ * d_usb_data_rate is used only to determine how often to poll for over- and under-runs.
+ * We defualt it to 1/2 of our best case. Classes derived from usrp_basic (e.g.,
+ * usrp_standard_tx and usrp_standard_rx) call set_usb_data_rate() to tell us the
+ * actual rate. This doesn't change our throughput, that's determined by the signal
+ * processing code in the FPGA (which we know nothing about), and the system limits
+ * determined by libusb, fusb_*, and the underlying drivers.
+ */
+ memset (d_fpga_shadows, 0, sizeof (d_fpga_shadows));
+
+ usrp_one_time_init ();
+
+ if (!usrp_load_standard_bits (which_board, false, fpga_filename, firmware_filename))
+ throw std::runtime_error ("usrp_basic/usrp_load_standard_bits");
+
+ struct usb_device *dev = usrp_find_device (which_board);
+ if (dev == 0){
+ fprintf (stderr, "usrp_basic: can't find usrp[%d]\n", which_board);
+ throw std::runtime_error ("usrp_basic/usrp_find_device");
+ }
+
+ if (!(usrp_usrp_p(dev) && usrp_hw_rev(dev) >= 1)){
+ fprintf (stderr, "usrp_basic: sorry, this code only works with USRP revs >= 1\n");
+ throw std::runtime_error ("usrp_basic/bad_rev");
+ }
+
+ if ((d_udh = open_interface (dev)) == 0)
+ throw std::runtime_error ("usrp_basic/open_interface");
+
+ // initialize registers that are common to rx and tx
+
+ if (!usrp_9862_write_many_all (d_udh, common_regs, sizeof (common_regs))){
+ fprintf (stderr, "usrp_basic: failed to init common AD9862 regs\n");
+ throw std::runtime_error ("usrp_basic/init_9862");
+ }
+
+ _write_fpga_reg (FR_MODE, 0); // ensure we're in normal mode
+ _write_fpga_reg (FR_DEBUG_EN, 0); // disable debug outputs
+}
+
+usrp_basic::~usrp_basic ()
+{
+ // shutdown_daughterboards(); // call from ~usrp_basic_{tx,rx}
+
+ d_db.resize(0); // forget db shared ptrs
+
+ if (d_udh)
+ usb_close (d_udh);
+}
+
+++ /dev/null
-/* -*- c++ -*- */
-/*
- * Copyright 2003,2004,2006,2009 Free Software Foundation, Inc.
- *
- * This file is part of GNU Radio
- *
- * GNU Radio is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 3, or (at your option)
- * any later version.
- *
- * GNU Radio is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with GNU Radio; see the file COPYING. If not, write to
- * the Free Software Foundation, Inc., 51 Franklin Street,
- * Boston, MA 02110-1301, USA.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "usrp/usrp_prims.h"
-#include "usrp_commands.h"
-#include "usrp_ids.h"
-#include "usrp_i2c_addr.h"
-#include "fpga_regs_common.h"
-#include "fpga_regs_standard.h"
-#include <libusb-1.0/libusb.h>
-#include <errno.h>
-#include <stdio.h>
-#include <unistd.h>
-#include <stdlib.h>
-#include <string.h>
-#include <ctype.h>
-#include <time.h> // FIXME should check with autoconf (nanosleep)
-#include <algorithm>
-#include <ad9862.h>
-#include <assert.h>
-
-extern "C" {
-#include "md5.h"
-};
-
-#define VERBOSE 0
-
-using namespace ad9862;
-
-static const int FIRMWARE_HASH_SLOT = 0;
-static const int FPGA_HASH_SLOT = 1;
-
-static const int hash_slot_addr[2] = {
- USRP_HASH_SLOT_0_ADDR,
- USRP_HASH_SLOT_1_ADDR
-};
-
-static const char *default_firmware_filename = "std.ihx";
-static const char *default_fpga_filename = "std_2rxhb_2tx.rbf";
-
-#include "std_paths.h"
-#include <stdio.h>
-
-static char *
-find_file (const char *filename, int hw_rev)
-{
- const char **sp = std_paths;
- static char path[1000];
- char *s;
-
- s = getenv("USRP_PATH");
- if (s) {
- snprintf (path, sizeof (path), "%s/rev%d/%s", s, hw_rev, filename);
- if (access (path, R_OK) == 0)
- return path;
- }
-
- while (*sp){
- snprintf (path, sizeof (path), "%s/rev%d/%s", *sp, hw_rev, filename);
- if (access (path, R_OK) == 0)
- return path;
- sp++;
- }
- return 0;
-}
-
-static const char *
-get_proto_filename(const std::string user_filename, const char *env_var, const char *def)
-{
- if (user_filename.length() != 0)
- return user_filename.c_str();
-
- char *s = getenv(env_var);
- if (s && *s)
- return s;
-
- return def;
-}
-
-
-static void power_down_9862s (struct libusb_device_handle *udh);
-
-libusb_context *
-usrp_one_time_init (bool new_context)
-{
-
- static bool first = true;
- libusb_context *ctx = NULL;
- int ret;
-
- // On first call create default context in addition to any new requested
- // context. The default context is probably useless in this form, but keep
- // it for now due to compatibility reasons.
-
- if (first) {
- first = false;
- if ((ret = libusb_init (NULL)) < 0)
- fprintf (stderr, "usrp: libusb_init failed %i\n", ret);
- }
-
- if (new_context) {
- if ((ret = libusb_init (&ctx)) < 0)
- fprintf (stderr, "usrp: libusb_init failed %i\n", ret);
- }
-
- return ctx;
-}
-
-void
-usrp_rescan ()
-{
- // deprecated?
-}
-
-// ----------------------------------------------------------------
-
-/*
- * q must be a real USRP, not an FX2. Return its hardware rev number.
- */
-int
-usrp_hw_rev (struct libusb_device *q)
-{
- struct libusb_device_descriptor desc;
- if (libusb_get_device_descriptor(q, &desc) < 0)
- fprintf (stderr, "usrp: libusb_get_device_descriptor failed\n");
-
- return desc.bcdDevice & 0x00FF;
-}
-
-/*
- * q must be a real USRP, not an FX2. Return true if it's configured.
- */
-static bool
-_usrp_configured_p (struct libusb_device *q)
-{
- struct libusb_device_descriptor desc;
- if (libusb_get_device_descriptor(q, &desc) < 0)
- fprintf (stderr, "usrp: libusb_get_device_descriptor failed\n");
-
- return (desc.bcdDevice & 0xFF00) != 0;
-}
-
-bool
-usrp_usrp_p (struct libusb_device *q)
-{
- struct libusb_device_descriptor desc;
- if (libusb_get_device_descriptor(q, &desc) < 0)
- fprintf (stderr, "usrp: libusb_get_device_descriptor failed\n");
-
- return (desc.idVendor == USB_VID_FSF
- && desc.idProduct == USB_PID_FSF_USRP);
-}
-
-bool
-usrp_fx2_p (struct libusb_device *q)
-{
- struct libusb_device_descriptor desc;
- if (libusb_get_device_descriptor(q, &desc) < 0)
- fprintf (stderr, "usrp: libusb_get_device_descriptor failed\n");
-
- return (desc.idVendor == USB_VID_CYPRESS
- && desc.idProduct == USB_PID_CYPRESS_FX2);
-}
-
-bool
-usrp_usrp0_p (struct libusb_device *q)
-{
- return usrp_usrp_p (q) && usrp_hw_rev (q) == 0;
-}
-
-bool
-usrp_usrp1_p (struct libusb_device *q)
-{
- return usrp_usrp_p (q) && usrp_hw_rev (q) == 1;
-}
-
-bool
-usrp_usrp2_p (struct libusb_device *q)
-{
- return usrp_usrp_p (q) && usrp_hw_rev (q) == 2;
-}
-
-
-bool
-usrp_unconfigured_usrp_p (struct libusb_device *q)
-{
- return usrp_usrp_p (q) && !_usrp_configured_p (q);
-}
-
-bool
-usrp_configured_usrp_p (struct libusb_device *q)
-{
- return usrp_usrp_p (q) && _usrp_configured_p (q);
-}
-
-// ----------------------------------------------------------------
-
-struct libusb_device *
-usrp_find_device (int nth, bool fx2_ok_p, libusb_context *ctx)
-{
- libusb_device **list;
-
- struct libusb_device *q;
- int n_found = 0;
-
-//usrp_one_time_init (false);
- assert (ctx != NULL);
-
- size_t cnt = libusb_get_device_list(ctx, &list);
- size_t i = 0;
-
- if (cnt < 0)
- fprintf(stderr, "usrp: libusb_get_device_list failed %d\n", cnt);
-
- for (i = 0; i < cnt; i++) {
- q = list[i];
- if (usrp_usrp_p (q) || (fx2_ok_p && usrp_fx2_p (q))) {
- if (n_found == nth) // return this one
- return q;
- n_found++; // keep looking
- }
- }
-
-/*
- * The list needs to be freed. Right just release it if nothing is found.
- */
-
- libusb_free_device_list(list, 1);
-
- return 0; // not found
-}
-
-static struct libusb_device_handle *
-usrp_open_interface (struct libusb_device *dev, int interface, int altinterface)
-{
- struct libusb_device_handle *udh;
- int ret;
-
- if (libusb_open (dev, &udh) < 0)
- return 0;
-
- if (dev != libusb_get_device (udh)){
- fprintf (stderr, "%s:%d: internal error!\n", __FILE__, __LINE__);
- abort ();
- }
-
- if ((ret = libusb_claim_interface (udh, interface)) < 0) {
- fprintf (stderr, "%s:usb_claim_interface: failed interface %d\n", __FUNCTION__,interface);
- fprintf (stderr, "%d\n", ret);
- libusb_close (udh);
- return 0;
- }
-
- if ((ret = libusb_set_interface_alt_setting (udh, interface,
- altinterface)) < 0) {
- fprintf (stderr, "%s:usb_set_alt_interface: failed\n", __FUNCTION__);
- fprintf (stderr, "%d\n", ret);
- libusb_release_interface (udh, interface);
- libusb_close (udh);
- return 0;
- }
-
- return udh;
-}
-
-struct libusb_device_handle *
-usrp_open_cmd_interface (struct libusb_device *dev)
-{
- return usrp_open_interface (dev, USRP_CMD_INTERFACE, USRP_CMD_ALTINTERFACE);
-}
-
-struct libusb_device_handle *
-usrp_open_rx_interface (struct libusb_device *dev)
-{
- return usrp_open_interface (dev, USRP_RX_INTERFACE, USRP_RX_ALTINTERFACE);
-}
-
-struct libusb_device_handle *
-usrp_open_tx_interface (struct libusb_device *dev)
-{
- return usrp_open_interface (dev, USRP_TX_INTERFACE, USRP_TX_ALTINTERFACE);
-}
-
-bool
-usrp_close_interface (struct libusb_device_handle *udh)
-{
- // returns void
- libusb_close(udh);
- return 0;
-}
-
-// ----------------------------------------------------------------
-// write internal ram using Cypress vendor extension
-
-static bool
-write_internal_ram (struct libusb_device_handle *udh, unsigned char *buf,
- int start_addr, size_t len)
-{
- int addr;
- int n;
- int a;
- int quanta = MAX_EP0_PKTSIZE;
-
- for (addr = start_addr; addr < start_addr + (int) len; addr += quanta){
- n = len + start_addr - addr;
- if (n > quanta)
- n = quanta;
-
- a = libusb_control_transfer (udh, 0x40, 0xA0,
- addr, 0, (unsigned char *)(buf + (addr - start_addr)), n, 1000);
-
- if (a < 0){
- fprintf(stderr,"write_internal_ram failed: %u\n", a);
- return false;
- }
- }
- return true;
-}
-
-// ----------------------------------------------------------------
-// whack the CPUCS register using the upload RAM vendor extension
-
-static bool
-reset_cpu (struct libusb_device_handle *udh, bool reset_p)
-{
- unsigned char v;
-
- if (reset_p)
- v = 1; // hold processor in reset
- else
- v = 0; // release reset
-
- return write_internal_ram (udh, &v, 0xE600, 1);
-}
-
-// ----------------------------------------------------------------
-// Load intel format file into cypress FX2 (8051)
-
-static bool
-_usrp_load_firmware (struct libusb_device_handle *udh, const char *filename,
- unsigned char hash[USRP_HASH_SIZE])
-{
- FILE *f = fopen (filename, "ra");
- if (f == 0){
- perror (filename);
- return false;
- }
-
- if (!reset_cpu (udh, true)) // hold CPU in reset while loading firmware
- goto fail;
-
-
- char s[1024];
- int length;
- int addr;
- int type;
- unsigned char data[256];
- unsigned char checksum, a;
- unsigned int b;
- int i;
-
- while (!feof(f)){
- fgets(s, sizeof (s), f); /* we should not use more than 263 bytes normally */
- if(s[0]!=':'){
- fprintf(stderr,"%s: invalid line: \"%s\"\n", filename, s);
- goto fail;
- }
- sscanf(s+1, "%02x", &length);
- sscanf(s+3, "%04x", &addr);
- sscanf(s+7, "%02x", &type);
-
- if(type==0){
-
- a=length+(addr &0xff)+(addr>>8)+type;
- for(i=0;i<length;i++){
- sscanf (s+9+i*2,"%02x", &b);
- data[i]=b;
- a=a+data[i];
- }
-
- sscanf (s+9+length*2,"%02x", &b);
- checksum=b;
- if (((a+checksum)&0xff)!=0x00){
- fprintf (stderr, " ** Checksum failed: got 0x%02x versus 0x%02x\n", (-a)&0xff, checksum);
- goto fail;
- }
- if (!write_internal_ram (udh, data, addr, length))
- goto fail;
- }
- else if (type == 0x01){ // EOF
- break;
- }
- else if (type == 0x02){
- fprintf(stderr, "Extended address: whatever I do with it?\n");
- fprintf (stderr, "%s: invalid line: \"%s\"\n", filename, s);
- goto fail;
- }
- }
-
- // we jam the hash value into the FX2 memory before letting
- // the cpu out of reset. When it comes out of reset it
- // may renumerate which will invalidate udh.
-
- if (!usrp_set_hash (udh, FIRMWARE_HASH_SLOT, hash))
- fprintf (stderr, "usrp: failed to write firmware hash slot\n");
-
- if (!reset_cpu (udh, false)) // take CPU out of reset
- goto fail;
-
- fclose (f);
- return true;
-
- fail:
- fclose (f);
- return false;
-}
-
-// ----------------------------------------------------------------
-// write vendor extension command to USRP
-
-static int
-write_cmd (struct libusb_device_handle *udh,
- int request, int value, int index,
- unsigned char *bytes, int len)
-{
- int requesttype = (request & 0x80) ? VRT_VENDOR_IN : VRT_VENDOR_OUT;
-
- int r = libusb_control_transfer(udh, requesttype, request, value, index,
- (unsigned char *) bytes, len, 1000);
-
- if (r < 0){
- // we get EPIPE if the firmware stalls the endpoint.
- if (r != LIBUSB_ERROR_PIPE) {
- fprintf (stderr, "libusb_control_transfer failed: %i\n", r);
- }
- }
-
- return r;
-}
-
-// ----------------------------------------------------------------
-// load fpga
-
-static bool
-_usrp_load_fpga (struct libusb_device_handle *udh, const char *filename,
- unsigned char hash[USRP_HASH_SIZE])
-{
- bool ok = true;
-
- FILE *fp = fopen (filename, "rb");
- if (fp == 0){
- perror (filename);
- return false;
- }
-
- unsigned char buf[MAX_EP0_PKTSIZE]; // 64 is max size of EP0 packet on FX2
- int n;
-
- usrp_set_led (udh, 1, 1); // led 1 on
-
-
- // reset FPGA (and on rev1 both AD9862's, thus killing clock)
- usrp_set_fpga_reset (udh, 1); // hold fpga in reset
-
- if (write_cmd (udh, VRQ_FPGA_LOAD, 0, FL_BEGIN, 0, 0) != 0)
- goto fail;
-
- while ((n = fread (buf, 1, sizeof (buf), fp)) > 0){
- if (write_cmd (udh, VRQ_FPGA_LOAD, 0, FL_XFER, buf, n) != n)
- goto fail;
- }
-
- if (write_cmd (udh, VRQ_FPGA_LOAD, 0, FL_END, 0, 0) != 0)
- goto fail;
-
- fclose (fp);
-
- if (!usrp_set_hash (udh, FPGA_HASH_SLOT, hash))
- fprintf (stderr, "usrp: failed to write fpga hash slot\n");
-
- // On the rev1 USRP, the {tx,rx}_{enable,reset} bits are
- // controlled over the serial bus, and hence aren't observed until
- // we've got a good fpga bitstream loaded.
-
- usrp_set_fpga_reset (udh, 0); // fpga out of master reset
-
- // now these commands will work
-
- ok &= usrp_set_fpga_tx_enable (udh, 0);
- ok &= usrp_set_fpga_rx_enable (udh, 0);
-
- ok &= usrp_set_fpga_tx_reset (udh, 1); // reset tx and rx paths
- ok &= usrp_set_fpga_rx_reset (udh, 1);
- ok &= usrp_set_fpga_tx_reset (udh, 0); // reset tx and rx paths
- ok &= usrp_set_fpga_rx_reset (udh, 0);
-
- if (!ok)
- fprintf (stderr, "usrp: failed to reset tx and/or rx path\n");
-
- // Manually reset all regs except master control to zero.
- // FIXME may want to remove this when we rework FPGA reset strategy.
- // In the mean while, this gets us reproducible behavior.
- for (int i = 0; i < FR_USER_0; i++){
- if (i == FR_MASTER_CTRL)
- continue;
- usrp_write_fpga_reg(udh, i, 0);
- }
-
- power_down_9862s (udh); // on the rev1, power these down!
- usrp_set_led (udh, 1, 0); // led 1 off
-
- return true;
-
- fail:
- power_down_9862s (udh); // on the rev1, power these down!
- fclose (fp);
- return false;
-}
-
-// ----------------------------------------------------------------
-
-bool
-usrp_set_led (struct libusb_device_handle *udh, int which, bool on)
-{
- int r = write_cmd (udh, VRQ_SET_LED, on, which, 0, 0);
-
- return r == 0;
-}
-
-bool
-usrp_set_hash (struct libusb_device_handle *udh, int which,
- const unsigned char hash[USRP_HASH_SIZE])
-{
- which &= 1;
-
- // we use the Cypress firmware down load command to jam it in.
- int r = libusb_control_transfer (udh, 0x40, 0xa0, hash_slot_addr[which], 0,
- (unsigned char *) hash, USRP_HASH_SIZE, 1000);
- return r == USRP_HASH_SIZE;
-}
-
-bool
-usrp_get_hash (struct libusb_device_handle *udh, int which,
- unsigned char hash[USRP_HASH_SIZE])
-{
- which &= 1;
-
- // we use the Cypress firmware upload command to fetch it.
- int r = libusb_control_transfer (udh, 0xc0, 0xa0, hash_slot_addr[which], 0,
- (unsigned char *) hash, USRP_HASH_SIZE, 1000);
- return r == USRP_HASH_SIZE;
-}
-
-static bool
-usrp_set_switch (struct libusb_device_handle *udh, int cmd_byte, bool on)
-{
- return write_cmd (udh, cmd_byte, on, 0, 0, 0) == 0;
-}
-
-
-static bool
-usrp1_fpga_write (struct libusb_device_handle *udh,
- int regno, int value)
-{
- // on the rev1 usrp, we use the generic spi_write interface
-
- unsigned char buf[4];
-
- buf[0] = (value >> 24) & 0xff; // MSB first
- buf[1] = (value >> 16) & 0xff;
- buf[2] = (value >> 8) & 0xff;
- buf[3] = (value >> 0) & 0xff;
-
- return usrp_spi_write (udh, 0x00 | (regno & 0x7f),
- SPI_ENABLE_FPGA,
- SPI_FMT_MSB | SPI_FMT_HDR_1,
- buf, sizeof (buf));
-}
-
-static bool
-usrp1_fpga_read (struct libusb_device_handle *udh,
- int regno, int *value)
-{
- *value = 0;
- unsigned char buf[4];
-
- bool ok = usrp_spi_read (udh, 0x80 | (regno & 0x7f),
- SPI_ENABLE_FPGA,
- SPI_FMT_MSB | SPI_FMT_HDR_1,
- buf, sizeof (buf));
-
- if (ok)
- *value = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
-
- return ok;
-}
-
-
-bool
-usrp_write_fpga_reg (struct libusb_device_handle *udh, int reg, int value)
-{
- switch (usrp_hw_rev (libusb_get_device (udh))){
- case 0: // not supported ;)
- abort();
-
- default:
- return usrp1_fpga_write (udh, reg, value);
- }
-}
-
-bool
-usrp_read_fpga_reg (struct libusb_device_handle *udh, int reg, int *value)
-{
- switch (usrp_hw_rev (libusb_get_device (udh))){
- case 0: // not supported ;)
- abort();
-
- default:
- return usrp1_fpga_read (udh, reg, value);
- }
-}
-
-bool
-usrp_set_fpga_reset (struct libusb_device_handle *udh, bool on)
-{
- return usrp_set_switch (udh, VRQ_FPGA_SET_RESET, on);
-}
-
-bool
-usrp_set_fpga_tx_enable (struct libusb_device_handle *udh, bool on)
-{
- return usrp_set_switch (udh, VRQ_FPGA_SET_TX_ENABLE, on);
-}
-
-bool
-usrp_set_fpga_rx_enable (struct libusb_device_handle *udh, bool on)
-{
- return usrp_set_switch (udh, VRQ_FPGA_SET_RX_ENABLE, on);
-}
-
-bool
-usrp_set_fpga_tx_reset (struct libusb_device_handle *udh, bool on)
-{
- return usrp_set_switch (udh, VRQ_FPGA_SET_TX_RESET, on);
-}
-
-bool
-usrp_set_fpga_rx_reset (struct libusb_device_handle *udh, bool on)
-{
- return usrp_set_switch (udh, VRQ_FPGA_SET_RX_RESET, on);
-}
-
-
-// ----------------------------------------------------------------
-// conditional load stuff
-
-static bool
-compute_hash (const char *filename, unsigned char hash[USRP_HASH_SIZE])
-{
- assert (USRP_HASH_SIZE == 16);
- memset (hash, 0, USRP_HASH_SIZE);
-
- FILE *fp = fopen (filename, "rb");
- if (fp == 0){
- perror (filename);
- return false;
- }
- int r = md5_stream (fp, hash);
- fclose (fp);
-
- return r == 0;
-}
-
-static usrp_load_status_t
-usrp_conditionally_load_something (struct libusb_device_handle *udh,
- const char *filename,
- bool force,
- int slot,
- bool loader (struct libusb_device_handle *,
- const char *,
- unsigned char [USRP_HASH_SIZE]))
-{
- unsigned char file_hash[USRP_HASH_SIZE];
- unsigned char usrp_hash[USRP_HASH_SIZE];
-
- if (access (filename, R_OK) != 0){
- perror (filename);
- return ULS_ERROR;
- }
-
- if (!compute_hash (filename, file_hash))
- return ULS_ERROR;
-
- if (!force
- && usrp_get_hash (udh, slot, usrp_hash)
- && memcmp (file_hash, usrp_hash, USRP_HASH_SIZE) == 0)
- return ULS_ALREADY_LOADED;
-
- bool r = loader (udh, filename, file_hash);
-
- if (!r)
- return ULS_ERROR;
-
- return ULS_OK;
-}
-
-usrp_load_status_t
-usrp_load_firmware (struct libusb_device_handle *udh,
- const char *filename,
- bool force)
-{
- return usrp_conditionally_load_something (udh, filename, force,
- FIRMWARE_HASH_SLOT,
- _usrp_load_firmware);
-}
-
-usrp_load_status_t
-usrp_load_fpga (struct libusb_device_handle *udh,
- const char *filename,
- bool force)
-{
- return usrp_conditionally_load_something (udh, filename, force,
- FPGA_HASH_SLOT,
- _usrp_load_fpga);
-}
-
-static libusb_device_handle *
-open_nth_cmd_interface (int nth, libusb_context *ctx)
-{
-
- struct libusb_device *udev = usrp_find_device (nth, false, ctx);
- if (udev == 0){
- fprintf (stderr, "usrp: failed to find usrp[%d]\n", nth);
- return 0;
- }
-
- struct libusb_device_handle *udh;
-
- udh = usrp_open_cmd_interface (udev);
- if (udh == 0){
- // FIXME this could be because somebody else has it open.
- // We should delay and retry...
- fprintf (stderr, "open_nth_cmd_interface: open_cmd_interface failed\n");
- return 0;
- }
-
- return udh;
- }
-
-static bool
-our_nanosleep (const struct timespec *delay)
-{
- struct timespec new_delay = *delay;
- struct timespec remainder;
-
- while (1){
- int r = nanosleep (&new_delay, &remainder);
- if (r == 0)
- return true;
- if (errno == EINTR)
- new_delay = remainder;
- else {
- perror ("nanosleep");
- return false;
- }
- }
-}
-
-static bool
-mdelay (int millisecs)
-{
- struct timespec ts;
- ts.tv_sec = millisecs / 1000;
- ts.tv_nsec = (millisecs - (1000 * ts.tv_sec)) * 1000000;
- return our_nanosleep (&ts);
-}
-
-usrp_load_status_t
-usrp_load_firmware_nth (int nth, const char *filename, bool force, libusb_context *ctx)
-{
- struct libusb_device_handle *udh = open_nth_cmd_interface (nth, ctx);
- if (udh == 0)
- return ULS_ERROR;
-
- usrp_load_status_t s = usrp_load_firmware (udh, filename, force);
- usrp_close_interface (udh);
-
- switch (s){
-
- case ULS_ALREADY_LOADED: // nothing changed...
- return ULS_ALREADY_LOADED;
- break;
-
- case ULS_OK:
- // we loaded firmware successfully.
-
- // It's highly likely that the board will renumerate (simulate a
- // disconnect/reconnect sequence), invalidating our current
- // handle.
-
- // FIXME. Turn this into a loop that rescans until we refind ourselves
-
- struct timespec t; // delay for 1 second
- t.tv_sec = 2;
- t.tv_nsec = 0;
- our_nanosleep (&t);
-
- return ULS_OK;
-
- default:
- case ULS_ERROR: // some kind of problem
- return ULS_ERROR;
- }
-}
-
-static void
-load_status_msg (usrp_load_status_t s, const char *type, const char *filename)
-{
- char *e = getenv("USRP_VERBOSE");
- bool verbose = e != 0;
-
- switch (s){
- case ULS_ERROR:
- fprintf (stderr, "usrp: failed to load %s %s.\n", type, filename);
- break;
-
- case ULS_ALREADY_LOADED:
- if (verbose)
- fprintf (stderr, "usrp: %s %s already loaded.\n", type, filename);
- break;
-
- case ULS_OK:
- if (verbose)
- fprintf (stderr, "usrp: %s %s loaded successfully.\n", type, filename);
- break;
- }
-}
-
-bool
-usrp_load_standard_bits (int nth, bool force,
- const std::string fpga_filename,
- const std::string firmware_filename,
- libusb_context *ctx)
-{
- usrp_load_status_t s;
- const char *filename;
- const char *proto_filename;
- int hw_rev;
-
- assert (ctx != NULL);
-
- // first, figure out what hardware rev we're dealing with
- {
- struct libusb_device *udev = usrp_find_device (nth, false, ctx);
- if (udev == 0){
- fprintf (stderr, "usrp: failed to find usrp[%d]\n", nth);
- return false;
- }
- hw_rev = usrp_hw_rev (udev);
- }
-
- // start by loading the firmware
-
- proto_filename = get_proto_filename(firmware_filename, "USRP_FIRMWARE",
- default_firmware_filename);
- filename = find_file(proto_filename, hw_rev);
- if (filename == 0){
- fprintf (stderr, "Can't find firmware: %s\n", proto_filename);
- return false;
- }
- s = usrp_load_firmware_nth (nth, filename, force, ctx);
- load_status_msg (s, "firmware", filename);
-
- if (s == ULS_ERROR)
- return false;
-
- // if we actually loaded firmware, we must reload fpga ...
- if (s == ULS_OK)
- force = true;
-
- // now move on to the fpga configuration bitstream
-
- proto_filename = get_proto_filename(fpga_filename, "USRP_FPGA",
- default_fpga_filename);
- filename = find_file (proto_filename, hw_rev);
- if (filename == 0){
- fprintf (stderr, "Can't find fpga bitstream: %s\n", proto_filename);
- return false;
- }
- struct libusb_device_handle *udh = open_nth_cmd_interface (nth, ctx);
- if (udh == 0)
- return false;
-
- s = usrp_load_fpga (udh, filename, force);
- usrp_close_interface (udh);
- load_status_msg (s, "fpga bitstream", filename);
-
- if (s == ULS_ERROR)
- return false;
-
- return true;
-}
-
-bool
-_usrp_get_status (struct libusb_device_handle *udh, int which, bool *trouble)
-{
- unsigned char status;
- *trouble = true;
-
- if (write_cmd (udh, VRQ_GET_STATUS, 0, which,
- &status, sizeof (status)) != sizeof (status))
- return false;
-
- *trouble = status;
- return true;
-}
-
-bool
-usrp_check_rx_overrun (struct libusb_device_handle *udh, bool *overrun_p)
-{
- return _usrp_get_status (udh, GS_RX_OVERRUN, overrun_p);
-}
-
-bool
-usrp_check_tx_underrun (struct libusb_device_handle *udh, bool *underrun_p)
-{
- return _usrp_get_status (udh, GS_TX_UNDERRUN, underrun_p);
-}
-
-
-bool
-usrp_i2c_write (struct libusb_device_handle *udh, int i2c_addr,
- const void *buf, int len)
-{
- if (len < 1 || len > MAX_EP0_PKTSIZE)
- return false;
-
- return write_cmd (udh, VRQ_I2C_WRITE, i2c_addr, 0,
- (unsigned char *) buf, len) == len;
-}
-
-
-bool
-usrp_i2c_read (struct libusb_device_handle *udh, int i2c_addr,
- void *buf, int len)
-{
- if (len < 1 || len > MAX_EP0_PKTSIZE)
- return false;
-
- return write_cmd (udh, VRQ_I2C_READ, i2c_addr, 0,
- (unsigned char *) buf, len) == len;
-}
-
-bool
-usrp_spi_write (struct libusb_device_handle *udh,
- int optional_header, int enables, int format,
- const void *buf, int len)
-{
- if (len < 0 || len > MAX_EP0_PKTSIZE)
- return false;
-
- return write_cmd (udh, VRQ_SPI_WRITE,
- optional_header,
- ((enables & 0xff) << 8) | (format & 0xff),
- (unsigned char *) buf, len) == len;
-}
-
-
-bool
-usrp_spi_read (struct libusb_device_handle *udh,
- int optional_header, int enables, int format,
- void *buf, int len)
-{
- if (len < 0 || len > MAX_EP0_PKTSIZE)
- return false;
-
- return write_cmd (udh, VRQ_SPI_READ,
- optional_header,
- ((enables & 0xff) << 8) | (format & 0xff),
- (unsigned char *) buf, len) == len;
-}
-
-bool
-usrp_9862_write (struct libusb_device_handle *udh, int which_codec,
- int regno, int value)
-{
- if (0)
- fprintf (stderr, "usrp_9862_write which = %d, reg = %2d, val = %3d (0x%02x)\n",
- which_codec, regno, value, value);
-
- unsigned char buf[1];
-
- buf[0] = value;
-
- return usrp_spi_write (udh, 0x00 | (regno & 0x3f),
- which_codec == 0 ? SPI_ENABLE_CODEC_A : SPI_ENABLE_CODEC_B,
- SPI_FMT_MSB | SPI_FMT_HDR_1,
- buf, 1);
-}
-
-bool
-usrp_9862_read (struct libusb_device_handle *udh, int which_codec,
- int regno, unsigned char *value)
-{
- return usrp_spi_read (udh, 0x80 | (regno & 0x3f),
- which_codec == 0 ? SPI_ENABLE_CODEC_A : SPI_ENABLE_CODEC_B,
- SPI_FMT_MSB | SPI_FMT_HDR_1,
- value, 1);
-}
-
-bool
-usrp_9862_write_many (struct libusb_device_handle *udh,
- int which_codec,
- const unsigned char *buf,
- int len)
-{
- if (len & 0x1)
- return false; // must be even
-
- bool result = true;
-
- while (len > 0){
- result &= usrp_9862_write (udh, which_codec, buf[0], buf[1]);
- len -= 2;
- buf += 2;
- }
-
- return result;
-}
-
-
-bool
-usrp_9862_write_many_all (struct libusb_device_handle *udh,
- const unsigned char *buf, int len)
-{
- // FIXME handle 2/2 and 4/4 versions
-
- bool result;
- result = usrp_9862_write_many (udh, 0, buf, len);
- result &= usrp_9862_write_many (udh, 1, buf, len);
- return result;
-}
-
-static void
-power_down_9862s (struct libusb_device_handle *udh)
-{
- static const unsigned char regs[] = {
- REG_RX_PWR_DN, 0x01, // everything
- REG_TX_PWR_DN, 0x0f, // pwr dn digital and analog_both
- REG_TX_MODULATOR, 0x00 // coarse & fine modulators disabled
- };
-
- switch (usrp_hw_rev (libusb_get_device (udh))){
- case 0:
- break;
-
- default:
- usrp_9862_write_many_all (udh, regs, sizeof (regs));
- break;
- }
-}
-
-
-
-static const int EEPROM_PAGESIZE = 16;
-
-bool
-usrp_eeprom_write (struct libusb_device_handle *udh, int i2c_addr,
- int eeprom_offset, const void *buf, int len)
-{
- unsigned char cmd[2];
- const unsigned char *p = (unsigned char *) buf;
-
- // The simplest thing that could possibly work:
- // all writes are single byte writes.
- //
- // We could speed this up using the page write feature,
- // but we write so infrequently, why bother...
-
- while (len-- > 0){
- cmd[0] = eeprom_offset++;
- cmd[1] = *p++;
- bool r = usrp_i2c_write (udh, i2c_addr, cmd, sizeof (cmd));
- mdelay (10); // delay 10ms worst case write time
- if (!r)
- return false;
- }
-
- return true;
-}
-
-bool
-usrp_eeprom_read (struct libusb_device_handle *udh, int i2c_addr,
- int eeprom_offset, void *buf, int len)
-{
- unsigned char *p = (unsigned char *) buf;
-
- // We setup a random read by first doing a "zero byte write".
- // Writes carry an address. Reads use an implicit address.
-
- unsigned char cmd[1];
- cmd[0] = eeprom_offset;
- if (!usrp_i2c_write (udh, i2c_addr, cmd, sizeof (cmd)))
- return false;
-
- while (len > 0){
- int n = std::min (len, MAX_EP0_PKTSIZE);
- if (!usrp_i2c_read (udh, i2c_addr, p, n))
- return false;
- len -= n;
- p += n;
- }
- return true;
-}
-
-// ----------------------------------------------------------------
-
-static bool
-slot_to_codec (int slot, int *which_codec)
-{
- *which_codec = 0;
-
- switch (slot){
- case SLOT_TX_A:
- case SLOT_RX_A:
- *which_codec = 0;
- break;
-
- case SLOT_TX_B:
- case SLOT_RX_B:
- *which_codec = 1;
- break;
-
- default:
- fprintf (stderr, "usrp_prims:slot_to_codec: invalid slot = %d\n", slot);
- return false;
- }
- return true;
-}
-
-static bool
-tx_slot_p (int slot)
-{
- switch (slot){
- case SLOT_TX_A:
- case SLOT_TX_B:
- return true;
-
- default:
- return false;
- }
-}
-
-bool
-usrp_write_aux_dac (struct libusb_device_handle *udh, int slot,
- int which_dac, int value)
-{
- int which_codec;
-
- if (!slot_to_codec (slot, &which_codec))
- return false;
-
- if (!(0 <= which_dac && which_dac < 4)){
- fprintf (stderr, "usrp_write_aux_dac: invalid dac = %d\n", which_dac);
- return false;
- }
-
- value &= 0x0fff; // mask to 12-bits
-
- if (which_dac == 3){
- // dac 3 is really 12-bits. Use value as is.
- bool r = true;
- r &= usrp_9862_write (udh, which_codec, 43, (value >> 4)); // most sig
- r &= usrp_9862_write (udh, which_codec, 42, (value & 0xf) << 4); // least sig
- return r;
- }
- else {
- // dac 0, 1, and 2 are really 8 bits.
- value = value >> 4; // shift value appropriately
- return usrp_9862_write (udh, which_codec, 36 + which_dac, value);
- }
-}
-
-
-bool
-usrp_read_aux_adc (struct libusb_device_handle *udh, int slot,
- int which_adc, int *value)
-{
- *value = 0;
- int which_codec;
-
- if (!slot_to_codec (slot, &which_codec))
- return false;
-
- if (!(0 <= which_codec && which_codec < 2)){
- fprintf (stderr, "usrp_read_aux_adc: invalid adc = %d\n", which_adc);
- return false;
- }
-
- unsigned char aux_adc_control =
- AUX_ADC_CTRL_REFSEL_A // on chip reference
- | AUX_ADC_CTRL_REFSEL_B; // on chip reference
-
- int rd_reg = 26; // base address of two regs to read for result
-
- // program the ADC mux bits
- if (tx_slot_p (slot))
- aux_adc_control |= AUX_ADC_CTRL_SELECT_A2 | AUX_ADC_CTRL_SELECT_B2;
- else {
- rd_reg += 2;
- aux_adc_control |= AUX_ADC_CTRL_SELECT_A1 | AUX_ADC_CTRL_SELECT_B1;
- }
-
- // I'm not sure if we can set the mux and issue a start conversion
- // in the same cycle, so let's do them one at a time.
-
- usrp_9862_write (udh, which_codec, 34, aux_adc_control);
-
- if (which_adc == 0)
- aux_adc_control |= AUX_ADC_CTRL_START_A;
- else {
- rd_reg += 4;
- aux_adc_control |= AUX_ADC_CTRL_START_B;
- }
-
- // start the conversion
- usrp_9862_write (udh, which_codec, 34, aux_adc_control);
-
- // read the 10-bit result back
- unsigned char v_lo = 0;
- unsigned char v_hi = 0;
- bool r = usrp_9862_read (udh, which_codec, rd_reg, &v_lo);
- r &= usrp_9862_read (udh, which_codec, rd_reg + 1, &v_hi);
-
- if (r)
- *value = ((v_hi << 2) | ((v_lo >> 6) & 0x3)) << 2; // format as 12-bit
-
- return r;
-}
-
-// ----------------------------------------------------------------
-
-static int slot_to_i2c_addr (int slot)
-{
- switch (slot){
- case SLOT_TX_A: return I2C_ADDR_TX_A;
- case SLOT_RX_A: return I2C_ADDR_RX_A;
- case SLOT_TX_B: return I2C_ADDR_TX_B;
- case SLOT_RX_B: return I2C_ADDR_RX_B;
- default: return -1;
- }
-}
-
-static void
-set_chksum (unsigned char *buf)
-{
- int sum = 0;
- unsigned int i;
- for (i = 0; i < DB_EEPROM_CLEN - 1; i++)
- sum += buf[i];
- buf[i] = -sum;
-}
-
-static usrp_dbeeprom_status_t
-read_dboard_eeprom (struct libusb_device_handle *udh,
- int slot_id, unsigned char *buf)
-{
- int i2c_addr = slot_to_i2c_addr (slot_id);
- if (i2c_addr == -1)
- return UDBE_BAD_SLOT;
-
- if (!usrp_eeprom_read (udh, i2c_addr, 0, buf, DB_EEPROM_CLEN))
- return UDBE_NO_EEPROM;
-
- if (buf[DB_EEPROM_MAGIC] != DB_EEPROM_MAGIC_VALUE)
- return UDBE_INVALID_EEPROM;
-
- int sum = 0;
- for (unsigned int i = 0; i < DB_EEPROM_CLEN; i++)
- sum += buf[i];
-
- if ((sum & 0xff) != 0)
- return UDBE_INVALID_EEPROM;
-
- return UDBE_OK;
-}
-
-usrp_dbeeprom_status_t
-usrp_read_dboard_eeprom (struct libusb_device_handle *udh,
- int slot_id, usrp_dboard_eeprom *eeprom)
-{
- unsigned char buf[DB_EEPROM_CLEN];
-
- memset (eeprom, 0, sizeof (*eeprom));
-
- usrp_dbeeprom_status_t s = read_dboard_eeprom (udh, slot_id, buf);
- if (s != UDBE_OK)
- return s;
-
- eeprom->id = (buf[DB_EEPROM_ID_MSB] << 8) | buf[DB_EEPROM_ID_LSB];
- eeprom->oe = (buf[DB_EEPROM_OE_MSB] << 8) | buf[DB_EEPROM_OE_LSB];
- eeprom->offset[0] = (buf[DB_EEPROM_OFFSET_0_MSB] << 8) | buf[DB_EEPROM_OFFSET_0_LSB];
- eeprom->offset[1] = (buf[DB_EEPROM_OFFSET_1_MSB] << 8) | buf[DB_EEPROM_OFFSET_1_LSB];
-
- return UDBE_OK;
-}
-
-bool
-usrp_write_dboard_offsets (struct libusb_device_handle *udh, int slot_id,
- short offset0, short offset1)
-{
- unsigned char buf[DB_EEPROM_CLEN];
-
- usrp_dbeeprom_status_t s = read_dboard_eeprom (udh, slot_id, buf);
- if (s != UDBE_OK)
- return false;
-
- buf[DB_EEPROM_OFFSET_0_LSB] = (offset0 >> 0) & 0xff;
- buf[DB_EEPROM_OFFSET_0_MSB] = (offset0 >> 8) & 0xff;
- buf[DB_EEPROM_OFFSET_1_LSB] = (offset1 >> 0) & 0xff;
- buf[DB_EEPROM_OFFSET_1_MSB] = (offset1 >> 8) & 0xff;
- set_chksum (buf);
-
- return usrp_eeprom_write (udh, slot_to_i2c_addr (slot_id),
- 0, buf, sizeof (buf));
-}
-
-std::string
-usrp_serial_number(struct libusb_device_handle *udh)
-{
- struct libusb_device_descriptor desc;
- if (libusb_get_device_descriptor(libusb_get_device(udh), &desc) < 0)
- fprintf (stderr, "usrp: libusb_get_device_descriptor failed\n");
-
- unsigned char iserial = desc.iSerialNumber;
- if (iserial == 0)
- return "";
-
- unsigned char buf[1024];
- if (libusb_get_string_descriptor_ascii(udh, iserial, buf, sizeof(buf)) < 0)
- return "";
-
- return (char*) buf;
-}
--- /dev/null
+/* -*- c++ -*- */
+/*
+ * Copyright 2003,2004,2006,2009 Free Software Foundation, Inc.
+ *
+ * This file is part of GNU Radio
+ *
+ * GNU Radio is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3, or (at your option)
+ * any later version.
+ *
+ * GNU Radio is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with GNU Radio; see the file COPYING. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "usrp/usrp_prims.h"
+#include "usrp_commands.h"
+#include "usrp_ids.h"
+#include "usrp_i2c_addr.h"
+#include "fpga_regs_common.h"
+#include "fpga_regs_standard.h"
+#include <errno.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+#include <time.h> // FIXME should check with autoconf (nanosleep)
+#include <algorithm>
+#include <ad9862.h>
+#include <assert.h>
+
+#if 1
+#include <usb.h>
+#else
+#include <libusb-1.0/libusb.h>
+#endif
+
+extern "C" {
+#include "md5.h"
+};
+
+#define VERBOSE 0
+
+using namespace ad9862;
+
+static const int FIRMWARE_HASH_SLOT = 0;
+static const int FPGA_HASH_SLOT = 1;
+
+static const int hash_slot_addr[2] = {
+ USRP_HASH_SLOT_0_ADDR,
+ USRP_HASH_SLOT_1_ADDR
+};
+
+static const char *default_firmware_filename = "std.ihx";
+static const char *default_fpga_filename = "std_2rxhb_2tx.rbf";
+
+/*
+ * Forward Declarations
+ */
+
+bool _usrp_configured_p (libusb_device *q);
+libusb_device_handle *usrp_open_interface(libusb_device *dev,
+ int interface,
+ int altinterface);
+bool write_internal_ram (libusb_device_handle *udh, unsigned char *buf,
+ int start_addr, size_t len);
+int write_cmd (libusb_device_handle *udh, int request, int value,
+ int index, unsigned char *bytes, int len);
+
+#include "std_paths.h"
+#include <stdio.h>
+
+char *
+find_file (const char *filename, int hw_rev)
+{
+ const char **sp = std_paths;
+ static char path[1000];
+ char *s;
+
+ s = getenv("USRP_PATH");
+ if (s) {
+ snprintf (path, sizeof (path), "%s/rev%d/%s", s, hw_rev, filename);
+ if (access (path, R_OK) == 0)
+ return path;
+ }
+
+ while (*sp){
+ snprintf (path, sizeof (path), "%s/rev%d/%s", *sp, hw_rev, filename);
+ if (access (path, R_OK) == 0)
+ return path;
+ sp++;
+ }
+ return 0;
+}
+
+const char *
+get_proto_filename(const std::string user_filename, const char *env_var, const char *def)
+{
+ if (user_filename.length() != 0)
+ return user_filename.c_str();
+
+ char *s = getenv(env_var);
+ if (s && *s)
+ return s;
+
+ return def;
+}
+
+
+void power_down_9862s (libusb_device_handle *udh);
+
+// ----------------------------------------------------------------
+
+bool
+usrp_usrp0_p (libusb_device *q)
+{
+ return usrp_usrp_p (q) && usrp_hw_rev (q) == 0;
+}
+
+bool
+usrp_usrp1_p (libusb_device *q)
+{
+ return usrp_usrp_p (q) && usrp_hw_rev (q) == 1;
+}
+
+bool
+usrp_usrp2_p (libusb_device *q)
+{
+ return usrp_usrp_p (q) && usrp_hw_rev (q) == 2;
+}
+
+
+bool
+usrp_unconfigured_usrp_p (libusb_device *q)
+{
+ return usrp_usrp_p (q) && !_usrp_configured_p (q);
+}
+
+bool
+usrp_configured_usrp_p (libusb_device *q)
+{
+ return usrp_usrp_p (q) && _usrp_configured_p (q);
+}
+
+libusb_device_handle *
+usrp_open_cmd_interface (libusb_device *dev)
+{
+ return usrp_open_interface (dev, USRP_CMD_INTERFACE, USRP_CMD_ALTINTERFACE);
+}
+
+libusb_device_handle *
+usrp_open_rx_interface (libusb_device *dev)
+{
+ return usrp_open_interface (dev, USRP_RX_INTERFACE, USRP_RX_ALTINTERFACE);
+}
+
+libusb_device_handle *
+usrp_open_tx_interface (libusb_device *dev)
+{
+ return usrp_open_interface (dev, USRP_TX_INTERFACE, USRP_TX_ALTINTERFACE);
+}
+
+
+// ----------------------------------------------------------------
+// whack the CPUCS register using the upload RAM vendor extension
+
+static bool
+reset_cpu (libusb_device_handle *udh, bool reset_p)
+{
+ unsigned char v;
+
+ if (reset_p)
+ v = 1; // hold processor in reset
+ else
+ v = 0; // release reset
+
+ return write_internal_ram (udh, &v, 0xE600, 1);
+}
+
+// ----------------------------------------------------------------
+// Load intel format file into cypress FX2 (8051)
+
+static bool
+_usrp_load_firmware (libusb_device_handle *udh, const char *filename,
+ unsigned char hash[USRP_HASH_SIZE])
+{
+ FILE *f = fopen (filename, "ra");
+ if (f == 0){
+ perror (filename);
+ return false;
+ }
+
+ if (!reset_cpu (udh, true)) // hold CPU in reset while loading firmware
+ goto fail;
+
+
+ char s[1024];
+ int length;
+ int addr;
+ int type;
+ unsigned char data[256];
+ unsigned char checksum, a;
+ unsigned int b;
+ int i;
+
+ while (!feof(f)){
+ fgets(s, sizeof (s), f); /* we should not use more than 263 bytes normally */
+ if(s[0]!=':'){
+ fprintf(stderr,"%s: invalid line: \"%s\"\n", filename, s);
+ goto fail;
+ }
+ sscanf(s+1, "%02x", &length);
+ sscanf(s+3, "%04x", &addr);
+ sscanf(s+7, "%02x", &type);
+
+ if(type==0){
+
+ a=length+(addr &0xff)+(addr>>8)+type;
+ for(i=0;i<length;i++){
+ sscanf (s+9+i*2,"%02x", &b);
+ data[i]=b;
+ a=a+data[i];
+ }
+
+ sscanf (s+9+length*2,"%02x", &b);
+ checksum=b;
+ if (((a+checksum)&0xff)!=0x00){
+ fprintf (stderr, " ** Checksum failed: got 0x%02x versus 0x%02x\n", (-a)&0xff, checksum);
+ goto fail;
+ }
+ if (!write_internal_ram (udh, data, addr, length))
+ goto fail;
+ }
+ else if (type == 0x01){ // EOF
+ break;
+ }
+ else if (type == 0x02){
+ fprintf(stderr, "Extended address: whatever I do with it?\n");
+ fprintf (stderr, "%s: invalid line: \"%s\"\n", filename, s);
+ goto fail;
+ }
+ }
+
+ // we jam the hash value into the FX2 memory before letting
+ // the cpu out of reset. When it comes out of reset it
+ // may renumerate which will invalidate udh.
+
+ if (!usrp_set_hash (udh, FIRMWARE_HASH_SLOT, hash))
+ fprintf (stderr, "usrp: failed to write firmware hash slot\n");
+
+ if (!reset_cpu (udh, false)) // take CPU out of reset
+ goto fail;
+
+ fclose (f);
+ return true;
+
+ fail:
+ fclose (f);
+ return false;
+}
+
+// ----------------------------------------------------------------
+// load fpga
+
+static bool
+_usrp_load_fpga (libusb_device_handle *udh, const char *filename,
+ unsigned char hash[USRP_HASH_SIZE])
+{
+ bool ok = true;
+
+ FILE *fp = fopen (filename, "rb");
+ if (fp == 0){
+ perror (filename);
+ return false;
+ }
+
+ unsigned char buf[MAX_EP0_PKTSIZE]; // 64 is max size of EP0 packet on FX2
+ int n;
+
+ usrp_set_led (udh, 1, 1); // led 1 on
+
+
+ // reset FPGA (and on rev1 both AD9862's, thus killing clock)
+ usrp_set_fpga_reset (udh, 1); // hold fpga in reset
+
+ if (write_cmd (udh, VRQ_FPGA_LOAD, 0, FL_BEGIN, 0, 0) != 0)
+ goto fail;
+
+ while ((n = fread (buf, 1, sizeof (buf), fp)) > 0){
+ if (write_cmd (udh, VRQ_FPGA_LOAD, 0, FL_XFER, buf, n) != n)
+ goto fail;
+ }
+
+ if (write_cmd (udh, VRQ_FPGA_LOAD, 0, FL_END, 0, 0) != 0)
+ goto fail;
+
+ fclose (fp);
+
+ if (!usrp_set_hash (udh, FPGA_HASH_SLOT, hash))
+ fprintf (stderr, "usrp: failed to write fpga hash slot\n");
+
+ // On the rev1 USRP, the {tx,rx}_{enable,reset} bits are
+ // controlled over the serial bus, and hence aren't observed until
+ // we've got a good fpga bitstream loaded.
+
+ usrp_set_fpga_reset (udh, 0); // fpga out of master reset
+
+ // now these commands will work
+
+ ok &= usrp_set_fpga_tx_enable (udh, 0);
+ ok &= usrp_set_fpga_rx_enable (udh, 0);
+
+ ok &= usrp_set_fpga_tx_reset (udh, 1); // reset tx and rx paths
+ ok &= usrp_set_fpga_rx_reset (udh, 1);
+ ok &= usrp_set_fpga_tx_reset (udh, 0); // reset tx and rx paths
+ ok &= usrp_set_fpga_rx_reset (udh, 0);
+
+ if (!ok)
+ fprintf (stderr, "usrp: failed to reset tx and/or rx path\n");
+
+ // Manually reset all regs except master control to zero.
+ // FIXME may want to remove this when we rework FPGA reset strategy.
+ // In the mean while, this gets us reproducible behavior.
+ for (int i = 0; i < FR_USER_0; i++){
+ if (i == FR_MASTER_CTRL)
+ continue;
+ usrp_write_fpga_reg(udh, i, 0);
+ }
+
+ power_down_9862s (udh); // on the rev1, power these down!
+ usrp_set_led (udh, 1, 0); // led 1 off
+
+ return true;
+
+ fail:
+ power_down_9862s (udh); // on the rev1, power these down!
+ fclose (fp);
+ return false;
+}
+
+// ----------------------------------------------------------------
+
+bool
+usrp_set_led (libusb_device_handle *udh, int which, bool on)
+{
+ int r = write_cmd (udh, VRQ_SET_LED, on, which, 0, 0);
+
+ return r == 0;
+}
+
+
+bool
+usrp_set_switch (libusb_device_handle *udh, int cmd_byte, bool on)
+{
+ return write_cmd (udh, cmd_byte, on, 0, 0, 0) == 0;
+}
+
+bool
+usrp1_fpga_write (libusb_device_handle *udh,
+ int regno, int value)
+{
+ // on the rev1 usrp, we use the generic spi_write interface
+
+ unsigned char buf[4];
+
+ buf[0] = (value >> 24) & 0xff; // MSB first
+ buf[1] = (value >> 16) & 0xff;
+ buf[2] = (value >> 8) & 0xff;
+ buf[3] = (value >> 0) & 0xff;
+
+ return usrp_spi_write (udh, 0x00 | (regno & 0x7f),
+ SPI_ENABLE_FPGA,
+ SPI_FMT_MSB | SPI_FMT_HDR_1,
+ buf, sizeof (buf));
+}
+
+bool
+usrp1_fpga_read (libusb_device_handle *udh,
+ int regno, int *value)
+{
+ *value = 0;
+ unsigned char buf[4];
+
+ bool ok = usrp_spi_read (udh, 0x80 | (regno & 0x7f),
+ SPI_ENABLE_FPGA,
+ SPI_FMT_MSB | SPI_FMT_HDR_1,
+ buf, sizeof (buf));
+
+ if (ok)
+ *value = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
+
+ return ok;
+}
+
+
+bool
+usrp_set_fpga_reset (libusb_device_handle *udh, bool on)
+{
+ return usrp_set_switch (udh, VRQ_FPGA_SET_RESET, on);
+}
+
+bool
+usrp_set_fpga_tx_enable (libusb_device_handle *udh, bool on)
+{
+ return usrp_set_switch (udh, VRQ_FPGA_SET_TX_ENABLE, on);
+}
+
+bool
+usrp_set_fpga_rx_enable (libusb_device_handle *udh, bool on)
+{
+ return usrp_set_switch (udh, VRQ_FPGA_SET_RX_ENABLE, on);
+}
+
+bool
+usrp_set_fpga_tx_reset (libusb_device_handle *udh, bool on)
+{
+ return usrp_set_switch (udh, VRQ_FPGA_SET_TX_RESET, on);
+}
+
+bool
+usrp_set_fpga_rx_reset (libusb_device_handle *udh, bool on)
+{
+ return usrp_set_switch (udh, VRQ_FPGA_SET_RX_RESET, on);
+}
+
+
+// ----------------------------------------------------------------
+// conditional load stuff
+
+static bool
+compute_hash (const char *filename, unsigned char hash[USRP_HASH_SIZE])
+{
+ assert (USRP_HASH_SIZE == 16);
+ memset (hash, 0, USRP_HASH_SIZE);
+
+ FILE *fp = fopen (filename, "rb");
+ if (fp == 0){
+ perror (filename);
+ return false;
+ }
+ int r = md5_stream (fp, hash);
+ fclose (fp);
+
+ return r == 0;
+}
+
+static usrp_load_status_t
+usrp_conditionally_load_something (libusb_device_handle *udh,
+ const char *filename,
+ bool force,
+ int slot,
+ bool loader (libusb_device_handle *,
+ const char *,
+ unsigned char [USRP_HASH_SIZE]))
+{
+ unsigned char file_hash[USRP_HASH_SIZE];
+ unsigned char usrp_hash[USRP_HASH_SIZE];
+
+ if (access (filename, R_OK) != 0){
+ perror (filename);
+ return ULS_ERROR;
+ }
+
+ if (!compute_hash (filename, file_hash))
+ return ULS_ERROR;
+
+ if (!force
+ && usrp_get_hash (udh, slot, usrp_hash)
+ && memcmp (file_hash, usrp_hash, USRP_HASH_SIZE) == 0)
+ return ULS_ALREADY_LOADED;
+
+ bool r = loader (udh, filename, file_hash);
+
+ if (!r)
+ return ULS_ERROR;
+
+ return ULS_OK;
+}
+
+usrp_load_status_t
+usrp_load_firmware (libusb_device_handle *udh,
+ const char *filename,
+ bool force)
+{
+ return usrp_conditionally_load_something (udh, filename, force,
+ FIRMWARE_HASH_SLOT,
+ _usrp_load_firmware);
+}
+
+usrp_load_status_t
+usrp_load_fpga (libusb_device_handle *udh,
+ const char *filename,
+ bool force)
+{
+ return usrp_conditionally_load_something (udh, filename, force,
+ FPGA_HASH_SLOT,
+ _usrp_load_fpga);
+}
+
+bool
+our_nanosleep (const struct timespec *delay)
+{
+ struct timespec new_delay = *delay;
+ struct timespec remainder;
+
+ while (1){
+ int r = nanosleep (&new_delay, &remainder);
+ if (r == 0)
+ return true;
+ if (errno == EINTR)
+ new_delay = remainder;
+ else {
+ perror ("nanosleep");
+ return false;
+ }
+ }
+}
+
+static bool
+mdelay (int millisecs)
+{
+ struct timespec ts;
+ ts.tv_sec = millisecs / 1000;
+ ts.tv_nsec = (millisecs - (1000 * ts.tv_sec)) * 1000000;
+ return our_nanosleep (&ts);
+}
+
+void
+load_status_msg (usrp_load_status_t s, const char *type, const char *filename)
+{
+ char *e = getenv("USRP_VERBOSE");
+ bool verbose = e != 0;
+
+ switch (s){
+ case ULS_ERROR:
+ fprintf (stderr, "usrp: failed to load %s %s.\n", type, filename);
+ break;
+
+ case ULS_ALREADY_LOADED:
+ if (verbose)
+ fprintf (stderr, "usrp: %s %s already loaded.\n", type, filename);
+ break;
+
+ case ULS_OK:
+ if (verbose)
+ fprintf (stderr, "usrp: %s %s loaded successfully.\n", type, filename);
+ break;
+ }
+}
+
+bool
+_usrp_get_status (libusb_device_handle *udh, int which, bool *trouble)
+{
+ unsigned char status;
+ *trouble = true;
+
+ if (write_cmd (udh, VRQ_GET_STATUS, 0, which,
+ &status, sizeof (status)) != sizeof (status))
+ return false;
+
+ *trouble = status;
+ return true;
+}
+
+bool
+usrp_check_rx_overrun (libusb_device_handle *udh, bool *overrun_p)
+{
+ return _usrp_get_status (udh, GS_RX_OVERRUN, overrun_p);
+}
+
+bool
+usrp_check_tx_underrun (libusb_device_handle *udh, bool *underrun_p)
+{
+ return _usrp_get_status (udh, GS_TX_UNDERRUN, underrun_p);
+}
+
+
+bool
+usrp_i2c_write (libusb_device_handle *udh, int i2c_addr,
+ const void *buf, int len)
+{
+ if (len < 1 || len > MAX_EP0_PKTSIZE)
+ return false;
+
+ return write_cmd (udh, VRQ_I2C_WRITE, i2c_addr, 0,
+ (unsigned char *) buf, len) == len;
+}
+
+
+bool
+usrp_i2c_read (libusb_device_handle *udh, int i2c_addr,
+ void *buf, int len)
+{
+ if (len < 1 || len > MAX_EP0_PKTSIZE)
+ return false;
+
+ return write_cmd (udh, VRQ_I2C_READ, i2c_addr, 0,
+ (unsigned char *) buf, len) == len;
+}
+
+bool
+usrp_spi_write (libusb_device_handle *udh,
+ int optional_header, int enables, int format,
+ const void *buf, int len)
+{
+ if (len < 0 || len > MAX_EP0_PKTSIZE)
+ return false;
+
+ return write_cmd (udh, VRQ_SPI_WRITE,
+ optional_header,
+ ((enables & 0xff) << 8) | (format & 0xff),
+ (unsigned char *) buf, len) == len;
+}
+
+
+bool
+usrp_spi_read (libusb_device_handle *udh,
+ int optional_header, int enables, int format,
+ void *buf, int len)
+{
+ if (len < 0 || len > MAX_EP0_PKTSIZE)
+ return false;
+
+ return write_cmd (udh, VRQ_SPI_READ,
+ optional_header,
+ ((enables & 0xff) << 8) | (format & 0xff),
+ (unsigned char *) buf, len) == len;
+}
+
+bool
+usrp_9862_write (libusb_device_handle *udh, int which_codec,
+ int regno, int value)
+{
+ if (0)
+ fprintf (stderr, "usrp_9862_write which = %d, reg = %2d, val = %3d (0x%02x)\n",
+ which_codec, regno, value, value);
+
+ unsigned char buf[1];
+
+ buf[0] = value;
+
+ return usrp_spi_write (udh, 0x00 | (regno & 0x3f),
+ which_codec == 0 ? SPI_ENABLE_CODEC_A : SPI_ENABLE_CODEC_B,
+ SPI_FMT_MSB | SPI_FMT_HDR_1,
+ buf, 1);
+}
+
+bool
+usrp_9862_read (libusb_device_handle *udh, int which_codec,
+ int regno, unsigned char *value)
+{
+ return usrp_spi_read (udh, 0x80 | (regno & 0x3f),
+ which_codec == 0 ? SPI_ENABLE_CODEC_A : SPI_ENABLE_CODEC_B,
+ SPI_FMT_MSB | SPI_FMT_HDR_1,
+ value, 1);
+}
+
+bool
+usrp_9862_write_many (libusb_device_handle *udh,
+ int which_codec,
+ const unsigned char *buf,
+ int len)
+{
+ if (len & 0x1)
+ return false; // must be even
+
+ bool result = true;
+
+ while (len > 0){
+ result &= usrp_9862_write (udh, which_codec, buf[0], buf[1]);
+ len -= 2;
+ buf += 2;
+ }
+
+ return result;
+}
+
+
+bool
+usrp_9862_write_many_all (libusb_device_handle *udh,
+ const unsigned char *buf, int len)
+{
+ // FIXME handle 2/2 and 4/4 versions
+
+ bool result;
+ result = usrp_9862_write_many (udh, 0, buf, len);
+ result &= usrp_9862_write_many (udh, 1, buf, len);
+ return result;
+}
+
+
+static const int EEPROM_PAGESIZE = 16;
+
+bool
+usrp_eeprom_write (libusb_device_handle *udh, int i2c_addr,
+ int eeprom_offset, const void *buf, int len)
+{
+ unsigned char cmd[2];
+ const unsigned char *p = (unsigned char *) buf;
+
+ // The simplest thing that could possibly work:
+ // all writes are single byte writes.
+ //
+ // We could speed this up using the page write feature,
+ // but we write so infrequently, why bother...
+
+ while (len-- > 0){
+ cmd[0] = eeprom_offset++;
+ cmd[1] = *p++;
+ bool r = usrp_i2c_write (udh, i2c_addr, cmd, sizeof (cmd));
+ mdelay (10); // delay 10ms worst case write time
+ if (!r)
+ return false;
+ }
+
+ return true;
+}
+
+bool
+usrp_eeprom_read (libusb_device_handle *udh, int i2c_addr,
+ int eeprom_offset, void *buf, int len)
+{
+ unsigned char *p = (unsigned char *) buf;
+
+ // We setup a random read by first doing a "zero byte write".
+ // Writes carry an address. Reads use an implicit address.
+
+ unsigned char cmd[1];
+ cmd[0] = eeprom_offset;
+ if (!usrp_i2c_write (udh, i2c_addr, cmd, sizeof (cmd)))
+ return false;
+
+ while (len > 0){
+ int n = std::min (len, MAX_EP0_PKTSIZE);
+ if (!usrp_i2c_read (udh, i2c_addr, p, n))
+ return false;
+ len -= n;
+ p += n;
+ }
+ return true;
+}
+
+// ----------------------------------------------------------------
+
+static bool
+slot_to_codec (int slot, int *which_codec)
+{
+ *which_codec = 0;
+
+ switch (slot){
+ case SLOT_TX_A:
+ case SLOT_RX_A:
+ *which_codec = 0;
+ break;
+
+ case SLOT_TX_B:
+ case SLOT_RX_B:
+ *which_codec = 1;
+ break;
+
+ default:
+ fprintf (stderr, "usrp_prims:slot_to_codec: invalid slot = %d\n", slot);
+ return false;
+ }
+ return true;
+}
+
+static bool
+tx_slot_p (int slot)
+{
+ switch (slot){
+ case SLOT_TX_A:
+ case SLOT_TX_B:
+ return true;
+
+ default:
+ return false;
+ }
+}
+
+bool
+usrp_write_aux_dac (libusb_device_handle *udh, int slot,
+ int which_dac, int value)
+{
+ int which_codec;
+
+ if (!slot_to_codec (slot, &which_codec))
+ return false;
+
+ if (!(0 <= which_dac && which_dac < 4)){
+ fprintf (stderr, "usrp_write_aux_dac: invalid dac = %d\n", which_dac);
+ return false;
+ }
+
+ value &= 0x0fff; // mask to 12-bits
+
+ if (which_dac == 3){
+ // dac 3 is really 12-bits. Use value as is.
+ bool r = true;
+ r &= usrp_9862_write (udh, which_codec, 43, (value >> 4)); // most sig
+ r &= usrp_9862_write (udh, which_codec, 42, (value & 0xf) << 4); // least sig
+ return r;
+ }
+ else {
+ // dac 0, 1, and 2 are really 8 bits.
+ value = value >> 4; // shift value appropriately
+ return usrp_9862_write (udh, which_codec, 36 + which_dac, value);
+ }
+}
+
+
+bool
+usrp_read_aux_adc (libusb_device_handle *udh, int slot,
+ int which_adc, int *value)
+{
+ *value = 0;
+ int which_codec;
+
+ if (!slot_to_codec (slot, &which_codec))
+ return false;
+
+ if (!(0 <= which_codec && which_codec < 2)){
+ fprintf (stderr, "usrp_read_aux_adc: invalid adc = %d\n", which_adc);
+ return false;
+ }
+
+ unsigned char aux_adc_control =
+ AUX_ADC_CTRL_REFSEL_A // on chip reference
+ | AUX_ADC_CTRL_REFSEL_B; // on chip reference
+
+ int rd_reg = 26; // base address of two regs to read for result
+
+ // program the ADC mux bits
+ if (tx_slot_p (slot))
+ aux_adc_control |= AUX_ADC_CTRL_SELECT_A2 | AUX_ADC_CTRL_SELECT_B2;
+ else {
+ rd_reg += 2;
+ aux_adc_control |= AUX_ADC_CTRL_SELECT_A1 | AUX_ADC_CTRL_SELECT_B1;
+ }
+
+ // I'm not sure if we can set the mux and issue a start conversion
+ // in the same cycle, so let's do them one at a time.
+
+ usrp_9862_write (udh, which_codec, 34, aux_adc_control);
+
+ if (which_adc == 0)
+ aux_adc_control |= AUX_ADC_CTRL_START_A;
+ else {
+ rd_reg += 4;
+ aux_adc_control |= AUX_ADC_CTRL_START_B;
+ }
+
+ // start the conversion
+ usrp_9862_write (udh, which_codec, 34, aux_adc_control);
+
+ // read the 10-bit result back
+ unsigned char v_lo = 0;
+ unsigned char v_hi = 0;
+ bool r = usrp_9862_read (udh, which_codec, rd_reg, &v_lo);
+ r &= usrp_9862_read (udh, which_codec, rd_reg + 1, &v_hi);
+
+ if (r)
+ *value = ((v_hi << 2) | ((v_lo >> 6) & 0x3)) << 2; // format as 12-bit
+
+ return r;
+}
+
+// ----------------------------------------------------------------
+
+static int slot_to_i2c_addr (int slot)
+{
+ switch (slot){
+ case SLOT_TX_A: return I2C_ADDR_TX_A;
+ case SLOT_RX_A: return I2C_ADDR_RX_A;
+ case SLOT_TX_B: return I2C_ADDR_TX_B;
+ case SLOT_RX_B: return I2C_ADDR_RX_B;
+ default: return -1;
+ }
+}
+
+static void
+set_chksum (unsigned char *buf)
+{
+ int sum = 0;
+ unsigned int i;
+ for (i = 0; i < DB_EEPROM_CLEN - 1; i++)
+ sum += buf[i];
+ buf[i] = -sum;
+}
+
+static usrp_dbeeprom_status_t
+read_dboard_eeprom (libusb_device_handle *udh,
+ int slot_id, unsigned char *buf)
+{
+ int i2c_addr = slot_to_i2c_addr (slot_id);
+ if (i2c_addr == -1)
+ return UDBE_BAD_SLOT;
+
+ if (!usrp_eeprom_read (udh, i2c_addr, 0, buf, DB_EEPROM_CLEN))
+ return UDBE_NO_EEPROM;
+
+ if (buf[DB_EEPROM_MAGIC] != DB_EEPROM_MAGIC_VALUE)
+ return UDBE_INVALID_EEPROM;
+
+ int sum = 0;
+ for (unsigned int i = 0; i < DB_EEPROM_CLEN; i++)
+ sum += buf[i];
+
+ if ((sum & 0xff) != 0)
+ return UDBE_INVALID_EEPROM;
+
+ return UDBE_OK;
+}
+
+usrp_dbeeprom_status_t
+usrp_read_dboard_eeprom (libusb_device_handle *udh,
+ int slot_id, usrp_dboard_eeprom *eeprom)
+{
+ unsigned char buf[DB_EEPROM_CLEN];
+
+ memset (eeprom, 0, sizeof (*eeprom));
+
+ usrp_dbeeprom_status_t s = read_dboard_eeprom (udh, slot_id, buf);
+ if (s != UDBE_OK)
+ return s;
+
+ eeprom->id = (buf[DB_EEPROM_ID_MSB] << 8) | buf[DB_EEPROM_ID_LSB];
+ eeprom->oe = (buf[DB_EEPROM_OE_MSB] << 8) | buf[DB_EEPROM_OE_LSB];
+ eeprom->offset[0] = (buf[DB_EEPROM_OFFSET_0_MSB] << 8) | buf[DB_EEPROM_OFFSET_0_LSB];
+ eeprom->offset[1] = (buf[DB_EEPROM_OFFSET_1_MSB] << 8) | buf[DB_EEPROM_OFFSET_1_LSB];
+
+ return UDBE_OK;
+}
+
+bool
+usrp_write_dboard_offsets (libusb_device_handle *udh, int slot_id,
+ short offset0, short offset1)
+{
+ unsigned char buf[DB_EEPROM_CLEN];
+
+ usrp_dbeeprom_status_t s = read_dboard_eeprom (udh, slot_id, buf);
+ if (s != UDBE_OK)
+ return false;
+
+ buf[DB_EEPROM_OFFSET_0_LSB] = (offset0 >> 0) & 0xff;
+ buf[DB_EEPROM_OFFSET_0_MSB] = (offset0 >> 8) & 0xff;
+ buf[DB_EEPROM_OFFSET_1_LSB] = (offset1 >> 0) & 0xff;
+ buf[DB_EEPROM_OFFSET_1_MSB] = (offset1 >> 8) & 0xff;
+ set_chksum (buf);
+
+ return usrp_eeprom_write (udh, slot_to_i2c_addr (slot_id),
+ 0, buf, sizeof (buf));
+}
--- /dev/null
+/* -*- c++ -*- */
+/*
+ * Copyright 2003,2004,2006,2009 Free Software Foundation, Inc.
+ *
+ * This file is part of GNU Radio
+ *
+ * GNU Radio is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3, or (at your option)
+ * any later version.
+ *
+ * GNU Radio is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with GNU Radio; see the file COPYING. If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "usrp/usrp_prims.h"
+#include "usrp_commands.h"
+#include "usrp_ids.h"
+#include "usrp_i2c_addr.h"
+#include "fpga_regs_common.h"
+#include "fpga_regs_standard.h"
+#include <usb.h>
+#include <errno.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+#include <time.h> // FIXME should check with autoconf (nanosleep)
+#include <algorithm>
+#include <ad9862.h>
+#include <assert.h>
+
+extern "C" {
+#include "md5.h"
+};
+
+#define VERBOSE 0
+
+using namespace ad9862;
+
+/*
+ * Forward Declarations
+ */
+
+bool our_nanosleep (const struct timespec *delay);
+const char *get_proto_filename (const std::string user_filename,
+ const char *env_var,
+ const char *def);
+char *find_file (const char *filename, int hw_rev);
+void load_status_msg (usrp_load_status_t s, const char *type,
+ const char *filename);
+bool usrp1_fpga_write (libusb_device_handle *udh, int regno, int value);
+bool usrp1_fpga_read (libusb_device_handle *udh, int regno, int *value);
+bool usrp_set_switch (libusb_device_handle *udh, int cmd_byte, bool on);
+
+bool usrp_set_fpga_reset (struct usb_dev_handle *udh, bool on);
+bool usrp_set_fpga_tx_enable (struct usb_dev_handle *udh, bool on);
+bool usrp_set_fpga_rx_enable (struct usb_dev_handle *udh, bool on);
+bool usrp_set_fpga_tx_reset (struct usb_dev_handle *udh, bool on);
+bool usrp_set_fpga_rx_reset (struct usb_dev_handle *udh, bool on);
+
+
+
+static const int FIRMWARE_HASH_SLOT = 0;
+static const int FPGA_HASH_SLOT = 1;
+
+static const int hash_slot_addr[2] = {
+ USRP_HASH_SLOT_0_ADDR,
+ USRP_HASH_SLOT_1_ADDR
+};
+
+static const char *default_firmware_filename = "std.ihx";
+static const char *default_fpga_filename = "std_2rxhb_2tx.rbf";
+
+#include "std_paths.h"
+#include <stdio.h>
+
+void
+usrp_one_time_init ()
+{
+ static bool first = true;
+
+ if (first){
+ first = false;
+ usb_init (); // usb library init
+ usb_find_busses ();
+ usb_find_devices ();
+ }
+}
+
+void
+usrp_rescan ()
+{
+ usb_find_busses ();
+ usb_find_devices ();
+}
+
+// ----------------------------------------------------------------
+
+/*
+ * q must be a real USRP, not an FX2. Return its hardware rev number.
+ */
+int
+usrp_hw_rev (struct usb_device *q)
+{
+ return q->descriptor.bcdDevice & 0x00FF;
+}
+
+/*
+ * q must be a real USRP, not an FX2. Return true if it's configured.
+ */
+static bool
+_usrp_configured_p (struct usb_device *q)
+{
+ return (q->descriptor.bcdDevice & 0xFF00) != 0;
+}
+
+bool
+usrp_usrp_p (struct usb_device *q)
+{
+ return (q->descriptor.idVendor == USB_VID_FSF
+ && q->descriptor.idProduct == USB_PID_FSF_USRP);
+}
+
+bool
+usrp_fx2_p (struct usb_device *q)
+{
+ return (q->descriptor.idVendor == USB_VID_CYPRESS
+ && q->descriptor.idProduct == USB_PID_CYPRESS_FX2);
+}
+
+// ----------------------------------------------------------------
+
+struct usb_device *
+usrp_find_device (int nth, bool fx2_ok_p, libusb_context *ctx)
+{
+ struct usb_bus *p;
+ struct usb_device *q;
+ int n_found = 0;
+
+ usrp_one_time_init ();
+
+ p = usb_get_busses();
+ while (p != NULL){
+ q = p->devices;
+ while (q != NULL){
+ if (usrp_usrp_p (q) || (fx2_ok_p && usrp_fx2_p (q))){
+ if (n_found == nth) // return this one
+ return q;
+ n_found++; // keep looking
+ }
+ q = q->next;
+ }
+ p = p->next;
+ }
+ return 0; // not found
+}
+
+struct usb_dev_handle *
+usrp_open_interface (struct usb_device *dev, int interface, int altinterface)
+{
+ struct usb_dev_handle *udh = usb_open (dev);
+ if (udh == 0)
+ return 0;
+
+ if (dev != usb_device (udh)){
+ fprintf (stderr, "%s:%d: internal error!\n", __FILE__, __LINE__);
+ abort ();
+ }
+
+#if defined(_WIN32) || defined(__WIN32__) || defined(__CYGWIN__)
+ // There's no get get_configuration function, and with some of the newer kernels
+ // setting the configuration, even if to the same value, hoses any other processes
+ // that have it open. Hence we opt to not set it at all (We've only
+ // got a single configuration anyway). This may hose the win32 stuff...
+
+ // Appears to be required for libusb-win32 and Cygwin -- dew 09/20/06
+ if (usb_set_configuration (udh, 1) < 0){
+ /*
+ * Ignore this error.
+ *
+ * Seems that something changed in drivers/usb/core/devio.c:proc_setconfig such that
+ * it returns -EBUSY if _any_ of the interfaces of a device are open.
+ * We've only got a single configuration, so setting it doesn't even seem
+ * like it should be required.
+ */
+ }
+#endif
+
+ if (usb_claim_interface (udh, interface) < 0){
+ fprintf (stderr, "%s:usb_claim_interface: failed interface %d\n", __FUNCTION__,interface);
+ fprintf (stderr, "%s\n", usb_strerror());
+ usb_close (udh);
+ return 0;
+ }
+
+ if (usb_set_altinterface (udh, altinterface) < 0){
+ fprintf (stderr, "%s:usb_set_alt_interface: failed\n", __FUNCTION__);
+ fprintf (stderr, "%s\n", usb_strerror());
+ usb_release_interface (udh, interface);
+ usb_close (udh);
+ return 0;
+ }
+
+ return udh;
+}
+
+bool
+usrp_close_interface (struct usb_dev_handle *udh)
+{
+ // we're assuming that closing an interface automatically releases it.
+ return usb_close (udh) == 0;
+}
+
+// ----------------------------------------------------------------
+// write internal ram using Cypress vendor extension
+
+bool
+write_internal_ram (struct usb_dev_handle *udh, unsigned char *buf,
+ int start_addr, size_t len)
+{
+ int addr;
+ int n;
+ int a;
+ int quanta = MAX_EP0_PKTSIZE;
+
+ for (addr = start_addr; addr < start_addr + (int) len; addr += quanta){
+ n = len + start_addr - addr;
+ if (n > quanta)
+ n = quanta;
+
+ a = usb_control_msg (udh, 0x40, 0xA0,
+ addr, 0, (char *)(buf + (addr - start_addr)), n, 1000);
+
+ if (a < 0){
+ fprintf(stderr,"write_internal_ram failed: %s\n", usb_strerror());
+ return false;
+ }
+ }
+ return true;
+}
+
+
+// ----------------------------------------------------------------
+// write vendor extension command to USRP
+
+int
+write_cmd (struct usb_dev_handle *udh,
+ int request, int value, int index,
+ unsigned char *bytes, int len)
+{
+ int requesttype = (request & 0x80) ? VRT_VENDOR_IN : VRT_VENDOR_OUT;
+
+ int r = usb_control_msg (udh, requesttype, request, value, index,
+ (char *) bytes, len, 1000);
+ if (r < 0){
+ // we get EPIPE if the firmware stalls the endpoint.
+ if (errno != EPIPE)
+ fprintf (stderr, "usb_control_msg failed: %s\n", usb_strerror ());
+ }
+
+ return r;
+}
+
+
+bool
+usrp_set_hash (struct usb_dev_handle *udh, int which,
+ const unsigned char hash[USRP_HASH_SIZE])
+{
+ which &= 1;
+
+ // we use the Cypress firmware down load command to jam it in.
+ int r = usb_control_msg (udh, 0x40, 0xa0, hash_slot_addr[which], 0,
+ (char *) hash, USRP_HASH_SIZE, 1000);
+ return r == USRP_HASH_SIZE;
+}
+
+bool
+usrp_get_hash (struct usb_dev_handle *udh, int which,
+ unsigned char hash[USRP_HASH_SIZE])
+{
+ which &= 1;
+
+ // we use the Cypress firmware upload command to fetch it.
+ int r = usb_control_msg (udh, 0xc0, 0xa0, hash_slot_addr[which], 0,
+ (char *) hash, USRP_HASH_SIZE, 1000);
+ return r == USRP_HASH_SIZE;
+}
+
+bool
+usrp_write_fpga_reg (struct usb_dev_handle *udh, int reg, int value)
+{
+ switch (usrp_hw_rev (usb_device (udh))){
+ case 0: // not supported ;)
+ abort();
+
+ default:
+ return usrp1_fpga_write (udh, reg, value);
+ }
+}
+
+bool
+usrp_read_fpga_reg (struct usb_dev_handle *udh, int reg, int *value)
+{
+ switch (usrp_hw_rev (usb_device (udh))){
+ case 0: // not supported ;)
+ abort();
+
+ default:
+ return usrp1_fpga_read (udh, reg, value);
+ }
+}
+
+
+
+
+static usb_dev_handle *
+open_nth_cmd_interface (int nth)
+{
+ struct usb_device *udev = usrp_find_device (nth);
+ if (udev == 0){
+ fprintf (stderr, "usrp: failed to find usrp[%d]\n", nth);
+ return 0;
+ }
+
+ struct usb_dev_handle *udh;
+
+ udh = usrp_open_cmd_interface (udev);
+ if (udh == 0){
+ // FIXME this could be because somebody else has it open.
+ // We should delay and retry...
+ fprintf (stderr, "open_nth_cmd_interface: open_cmd_interface failed\n");
+ usb_strerror ();
+ return 0;
+ }
+
+ return udh;
+}
+
+
+usrp_load_status_t
+usrp_load_firmware_nth (int nth, const char *filename, bool force, libusb_context *ctx){
+ struct usb_dev_handle *udh = open_nth_cmd_interface (nth);
+ if (udh == 0)
+ return ULS_ERROR;
+
+ usrp_load_status_t s = usrp_load_firmware (udh, filename, force);
+ usrp_close_interface (udh);
+
+ switch (s){
+
+ case ULS_ALREADY_LOADED: // nothing changed...
+ return ULS_ALREADY_LOADED;
+ break;
+
+ case ULS_OK:
+ // we loaded firmware successfully.
+
+ // It's highly likely that the board will renumerate (simulate a
+ // disconnect/reconnect sequence), invalidating our current
+ // handle.
+
+ // FIXME. Turn this into a loop that rescans until we refind ourselves
+
+ struct timespec t; // delay for 1 second
+ t.tv_sec = 2;
+ t.tv_nsec = 0;
+ our_nanosleep (&t);
+
+ usb_find_busses (); // rescan busses and devices
+ usb_find_devices ();
+
+ return ULS_OK;
+
+ default:
+ case ULS_ERROR: // some kind of problem
+ return ULS_ERROR;
+ }
+}
+
+bool
+usrp_load_standard_bits (int nth, bool force,
+ const std::string fpga_filename,
+ const std::string firmware_filename,
+ libusb_context *ctx)
+{
+ usrp_load_status_t s;
+ const char *filename;
+ const char *proto_filename;
+ int hw_rev;
+
+ // first, figure out what hardware rev we're dealing with
+ {
+ struct usb_device *udev = usrp_find_device (nth);
+ if (udev == 0){
+ fprintf (stderr, "usrp: failed to find usrp[%d]\n", nth);
+ return false;
+ }
+ hw_rev = usrp_hw_rev (udev);
+ }
+
+ // start by loading the firmware
+
+ proto_filename = get_proto_filename(firmware_filename, "USRP_FIRMWARE",
+ default_firmware_filename);
+ filename = find_file(proto_filename, hw_rev);
+ if (filename == 0){
+ fprintf (stderr, "Can't find firmware: %s\n", proto_filename);
+ return false;
+ }
+
+ s = usrp_load_firmware_nth (nth, filename, force);
+ load_status_msg (s, "firmware", filename);
+
+ if (s == ULS_ERROR)
+ return false;
+
+ // if we actually loaded firmware, we must reload fpga ...
+ if (s == ULS_OK)
+ force = true;
+
+ // now move on to the fpga configuration bitstream
+
+ proto_filename = get_proto_filename(fpga_filename, "USRP_FPGA",
+ default_fpga_filename);
+ filename = find_file (proto_filename, hw_rev);
+ if (filename == 0){
+ fprintf (stderr, "Can't find fpga bitstream: %s\n", proto_filename);
+ return false;
+ }
+
+ struct usb_dev_handle *udh = open_nth_cmd_interface (nth);
+ if (udh == 0)
+ return false;
+
+ s = usrp_load_fpga (udh, filename, force);
+ usrp_close_interface (udh);
+ load_status_msg (s, "fpga bitstream", filename);
+
+ if (s == ULS_ERROR)
+ return false;
+
+ return true;
+}
+
+void
+power_down_9862s (struct usb_dev_handle *udh)
+{
+ static const unsigned char regs[] = {
+ REG_RX_PWR_DN, 0x01, // everything
+ REG_TX_PWR_DN, 0x0f, // pwr dn digital and analog_both
+ REG_TX_MODULATOR, 0x00 // coarse & fine modulators disabled
+ };
+
+ switch (usrp_hw_rev (usb_device (udh))){
+ case 0:
+ break;
+
+ default:
+ usrp_9862_write_many_all (udh, regs, sizeof (regs));
+ break;
+ }
+}
+
+
+std::string
+usrp_serial_number(struct usb_dev_handle *udh)
+{
+ unsigned char iserial = usb_device(udh)->descriptor.iSerialNumber;
+ if (iserial == 0)
+ return "";
+
+ char buf[1024];
+ if (usb_get_string_simple(udh, iserial, buf, sizeof(buf)) < 0)
+ return "";
+
+ return buf;
+}
projects / debian / gnuradio / commitdiff