retval = target_read_u32(target, NUMICRO_FLASH_ISPTRG, &status);
if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("status: 0x%" PRIx32 "", status);
+ LOG_DEBUG("status: 0x%" PRIx32 "", status);
if ((status & (ISPTRG_ISPGO)) == 0)
break;
if (timeout-- <= 0) {
retval = target_read_u32(target, NUMICRO_FLASH_ISPTRG, &status);
if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("status: 0x%" PRIx32 "", status);
+ LOG_DEBUG("status: 0x%" PRIx32 "", status);
if (status == 0)
break;
if (timeout-- <= 0) {
retval = target_read_u32(target, NUMICRO_FLASH_ISPTRG, &status);
if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("status: 0x%" PRIx32 "", status);
+ LOG_DEBUG("status: 0x%" PRIx32 "", status);
if (status == 0)
break;
if (timeout-- <= 0) {
uint32_t cp15_opcode, uint32_t address, uint32_t *value)
{
struct arm *arm = target_to_arm(target);
- uint32_t *regs_p[1];
- uint32_t regs[2];
+ uint32_t *regs_p[16];
+ uint32_t regs[16];
uint32_t cp15c15 = 0x0;
struct reg *r = arm->core_cache->reg_list;
{
uint32_t cp15c15 = 0x0;
struct arm *arm = target_to_arm(target);
- uint32_t regs[2];
+ uint32_t regs[16];
struct reg *r = arm->core_cache->reg_list;
/* load value, address into R0, R1 */