const char *name;
};
-/* Option constants for bizarre disfunctionality and real features
+/* Option constants for bizarre dysfunctionality and real features
*/
enum {
/* Chip can not auto increment pages */
struct kinetis_chip *k_chip = k_bank->k_chip;
int result;
- /* suprisingly blank check does not work in VLPR and HSRUN modes */
+ /* surprisingly blank check does not work in VLPR and HSRUN modes */
result = kinetis_check_run_mode(k_chip);
if (result != ERROR_OK)
return result;
#define QSPI_W_EN (0x1)
#define QSPI_SS_DISABLE (0x0)
#define QSPI_SS_ENABLE (0x1)
-#define WRITE_DISBALE (0x0)
+#define WRITE_DISABLE (0x0)
#define WRITE_ENABLE (0x1)
#define QSPI_TIMEOUT (1000)
#define P4_SECTOR_LENGTH 0x1000
#define P4_ALGO_ENTRY_ADDR 0x01000110
-/* MSP432E4 flash paramters */
+/* MSP432E4 flash parameters */
#define E4_FLASH_BASE FLASH_BASE
#define E4_FLASH_SIZE 0x100000
#define E4_SECTOR_LENGTH 0x4000
* RM reads: Code running from code region 1 will not be able to write
* to code region 0.
* Unfortunately the flash loader running from RAM can write to both
- * code regions whithout any hint the protection is violated.
+ * code regions without any hint the protection is violated.
*
* Update protection state and check if any flash sector to be written
* is protected. */
bool octo;
struct flash_device dev;
uint32_t io_base;
- uint32_t saved_cr; /* in particalar FSEL, DFM bit mask in QUADSPI_CR *AND* OCTOSPI_CR */
+ uint32_t saved_cr; /* in particular FSEL, DFM bit mask in QUADSPI_CR *AND* OCTOSPI_CR */
uint32_t saved_ccr; /* different meaning for QUADSPI and OCTOSPI */
uint32_t saved_tcr; /* only for OCTOSPI */
uint32_t saved_ir; /* only for OCTOSPI */