- out_cr1("setup recv 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
- break;
- case 2:
- /* Clear any pending ADDR bit */
- out_cr1("setup recv 2", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_POS));
- if (in_sr1("clear addr", stm_i2c) & (1 << STM_I2C_SR1_ADDR))
- in_sr2("clear addr", stm_i2c);
- out_cr1("setup recv 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
- break;
- default:
-// out_cr1("setup recv 2", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_ACK) | (1 << STM_I2C_CR1_POS));
- out_cr1("setup recv 2", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_ACK));
+
+ /* Enable interrupts to transfer the byte */
+ out_cr2("setup recv 1", stm_i2c,
+ AO_STM_I2C_CR2 |
+ (1 << STM_I2C_CR2_ITEVTEN) |
+ (1 << STM_I2C_CR2_ITERREN) |
+ (1 << STM_I2C_CR2_ITBUFEN));
+ if (stop)
+ out_cr1("setup recv 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
+
+ ao_alarm(1);
+ cli();
+ while (ao_i2c_recv_len[index])
+ if (ao_sleep(&ao_i2c_recv_len[index]))
+ break;
+ sei();
+ ret = ao_i2c_recv_len[index] == 0;
+ ao_clear_alarm();
+ } else {
+ uint8_t rx_dma_index = ao_i2c_stm_info[index].rx_dma_index;
+ ao_dma_set_transfer(rx_dma_index,
+ &stm_i2c->dr,
+ block,
+ len,
+ (0 << STM_DMA_CCR_MEM2MEM) |
+ (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
+ (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
+ (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
+ (1 << STM_DMA_CCR_MINC) |
+ (0 << STM_DMA_CCR_PINC) |
+ (0 << STM_DMA_CCR_CIRC) |
+ (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
+ out_cr1("recv > 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_ACK));
+ out_cr2("recv > 1", stm_i2c, AO_STM_I2C_CR2 |
+ (1 << STM_I2C_CR2_DMAEN) | (1 << STM_I2C_CR2_LAST));