+#define CSR_DCSR_CAUSE 0x1c0
+/*
+ * ebreak: An {\tt ebreak} instruction was executed.
+ */
+#define CSR_DCSR_CAUSE_EBREAK 1
+/*
+ * trigger: A Trigger Module trigger fired with action=1.
+ */
+#define CSR_DCSR_CAUSE_TRIGGER 2
+/*
+ * haltreq: The debugger requested entry to Debug Mode using \FdmDmcontrolHaltreq.
+ */
+#define CSR_DCSR_CAUSE_HALTREQ 3
+/*
+ * step: The hart single stepped because \FcsrDcsrStep was set.
+ */
+#define CSR_DCSR_CAUSE_STEP 4
+/*
+ * resethaltreq: The hart halted directly out of reset due to \Fresethaltreq. It
+ * is also acceptable to report 3 when this happens.
+ */
+#define CSR_DCSR_CAUSE_RESETHALTREQ 5
+/*
+ * group: The hart halted because it's part of a halt group.
+ * Harts may report 3 for this cause instead.
+ */
+#define CSR_DCSR_CAUSE_GROUP 6
+/*
+ * Other values are reserved for future use.
+ */