The ADC requires a bunch of poking to get it started.
Signed-off-by: Keith Packard <keithp@keithp.com>
static uint8_t ao_adc_ready;
static uint8_t ao_adc_ready;
-#define AO_ADC_CR2_VAL ((HAS_ADC_TEMP << STM_ADC_CR2_TSVREF) | \
- (0 << STM_ADC_CR2_SWSTART) | \
+#define AO_ADC_CR2_VAL(start) ((HAS_ADC_TEMP << STM_ADC_CR2_TSVREF) | \
+ ((start) << STM_ADC_CR2_SWSTART) | \
(0 << STM_ADC_CR2_JWSTART) | \
(0 << STM_ADC_CR2_EXTTRIG) | \
(0 << STM_ADC_CR2_JWSTART) | \
(0 << STM_ADC_CR2_EXTTRIG) | \
- (0 << STM_ADC_CR2_EXTSEL) | \
- (0 << STM_ADC_CR2_JEXTTRIG) | \
+ (STM_ADC_CR2_EXTSEL_SWSTART << STM_ADC_CR2_EXTSEL) | \
+ (0 << STM_ADC_CR2_JEXTTRIG) | \
(0 << STM_ADC_CR2_JEXTSEL) | \
(0 << STM_ADC_CR2_ALIGN) | \
(1 << STM_ADC_CR2_DMA) | \
(0 << STM_ADC_CR2_JEXTSEL) | \
(0 << STM_ADC_CR2_ALIGN) | \
(1 << STM_ADC_CR2_DMA) | \
(void) index;
ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
ao_adc_ready = 1;
(void) index;
ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
ao_adc_ready = 1;
+ /* Turn the ADC back off */
+ stm_adc1.cr2 = 0;
ao_wakeup((void *) &ao_adc_ready);
}
ao_wakeup((void *) &ao_adc_ready);
}
ao_adc_poll(struct ao_adc *packet)
{
ao_adc_ready = 0;
ao_adc_poll(struct ao_adc *packet)
{
ao_adc_ready = 0;
ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
(void *) packet,
AO_NUM_ADC,
(0 << STM_DMA_CCR_MEM2MEM) |
(void *) packet,
AO_NUM_ADC,
(0 << STM_DMA_CCR_MEM2MEM) |
ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
- stm_adc.cr2 = AO_ADC_CR2_VAL | (1 << STM_ADC_CR2_SWSTART);
+ stm_adc1.cr2 = AO_ADC_CR2_VAL(0);
+ ao_delay(AO_MS_TO_TICKS(10));
+ stm_adc1.cr2 = AO_ADC_CR2_VAL(0);
+ ao_delay(AO_MS_TO_TICKS(10));
+ stm_adc1.cr2 = AO_ADC_CR2_VAL(1);
stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
/* Turn off ADC during configuration */
stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
/* Turn off ADC during configuration */
- stm_adc.cr1 = ((0 << STM_ADC_CR1_AWDEN ) |
+ stm_adc1.cr1 = ((0 << STM_ADC_CR1_AWDEN ) |
(0 << STM_ADC_CR1_JAWDEN ) |
(STM_ADC_CR1_DUALMOD_INDEPENDENT << STM_ADC_CR1_DUALMOD ) |
(0 << STM_ADC_CR1_DISCNUM ) |
(0 << STM_ADC_CR1_JAWDEN ) |
(STM_ADC_CR1_DUALMOD_INDEPENDENT << STM_ADC_CR1_DUALMOD ) |
(0 << STM_ADC_CR1_DISCNUM ) |
(0 << STM_ADC_CR1_AWDCH ));
/* 384 cycle sample time for everyone */
(0 << STM_ADC_CR1_AWDCH ));
/* 384 cycle sample time for everyone */
- stm_adc.smpr1 = 0x00ffffff;
- stm_adc.smpr2 = 0x3fffffff;
+ stm_adc1.smpr1 = 0x00ffffff;
+ stm_adc1.smpr2 = 0x3fffffff;
- stm_adc.sqr1 = ((AO_NUM_ADC - 1) << 20);
+ stm_adc1.sqr1 = ((AO_NUM_ADC - 1) << 20);
- stm_adc.sqr3 |= (AO_ADC_SQ1 << 0);
+ stm_adc1.sqr3 |= (AO_ADC_SQ1 << 0);
#endif
#if AO_NUM_ADC > 1
#endif
#if AO_NUM_ADC > 1
- stm_adc.sqr3 |= (AO_ADC_SQ2 << 5);
+ stm_adc1.sqr3 |= (AO_ADC_SQ2 << 5);
#endif
#if AO_NUM_ADC > 2
#endif
#if AO_NUM_ADC > 2
- stm_adc.sqr3 |= (AO_ADC_SQ3 << 10);
+ stm_adc1.sqr3 |= (AO_ADC_SQ3 << 10);
#endif
#if AO_NUM_ADC > 3
#endif
#if AO_NUM_ADC > 3
- stm_adc.sqr3 |= (AO_ADC_SQ4 << 15);
+ stm_adc1.sqr3 |= (AO_ADC_SQ4 << 15);
#endif
#if AO_NUM_ADC > 4
#endif
#if AO_NUM_ADC > 4
- stm_adc.sqr3 |= (AO_ADC_SQ5 << 20);
+ stm_adc1.sqr3 |= (AO_ADC_SQ5 << 20);
#endif
#if AO_NUM_ADC > 5
#endif
#if AO_NUM_ADC > 5
- stm_adc.sqr3 |= (AO_ADC_SQ6 << 25);
+ stm_adc1.sqr3 |= (AO_ADC_SQ6 << 25);
#endif
#if AO_NUM_ADC > 6
#endif
#if AO_NUM_ADC > 6
- stm_adc.sqr2 |= (AO_ADC_SQ7 << 0);
+ stm_adc1.sqr2 |= (AO_ADC_SQ7 << 0);
#endif
#if AO_NUM_ADC > 7
#endif
#if AO_NUM_ADC > 7
- stm_adc.sqr2 |= (AO_ADC_SQ8 << 5);
+ stm_adc1.sqr2 |= (AO_ADC_SQ8 << 5);
#endif
#if AO_NUM_ADC > 8
#endif
#if AO_NUM_ADC > 8
- stm_adc.sqr2 |= (AO_ADC_SQ9 << 10);
+ stm_adc1.sqr2 |= (AO_ADC_SQ9 << 10);
#endif
#if AO_NUM_ADC > 9
#endif
#if AO_NUM_ADC > 9
- stm_adc.sqr2 |= (AO_ADC_SQ10 << 15);
+ stm_adc1.sqr2 |= (AO_ADC_SQ10 << 15);
#endif
#if AO_NUM_ADC > 10
#endif
#if AO_NUM_ADC > 10
- stm_adc.sqr2 |= (AO_ADC_SQ11 << 20);
+ stm_adc1.sqr2 |= (AO_ADC_SQ11 << 20);
#endif
#if AO_NUM_ADC > 11
#endif
#if AO_NUM_ADC > 11
- stm_adc.sqr2 |= (AO_ADC_SQ12 << 25);
+ stm_adc1.sqr2 |= (AO_ADC_SQ12 << 25);
#endif
#if AO_NUM_ADC > 12
#endif
#if AO_NUM_ADC > 12
- stm_adc.sqr1 |= (AO_ADC_SQ13 << 0);
+ stm_adc1.sqr1 |= (AO_ADC_SQ13 << 0);
#endif
#if AO_NUM_ADC > 13
#endif
#if AO_NUM_ADC > 13
- stm_adc.sqr1 |= (AO_ADC_SQ14 << 5);
+ stm_adc1.sqr1 |= (AO_ADC_SQ14 << 5);
#endif
#if AO_NUM_ADC > 14
#endif
#if AO_NUM_ADC > 14
- stm_adc.sqr1 |= (AO_ADC_SQ15 << 10);
+ stm_adc1.sqr1 |= (AO_ADC_SQ15 << 10);
#endif
#if AO_NUM_ADC > 15
#endif
#if AO_NUM_ADC > 15
- stm_adc.sqr1 |= (AO_ADC_SQ16 << 15);
+ stm_adc1.sqr1 |= (AO_ADC_SQ16 << 15);
#endif
#if AO_NUM_ADC > 15
#error "too many ADC channels"
#endif
/* Clear any stale status bits */
#endif
#if AO_NUM_ADC > 15
#error "too many ADC channels"
#endif
/* Clear any stale status bits */
ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
- /* Turn on the ADC so that it is ready to convert */
-
- stm_adc.cr2 = AO_ADC_CR2_VAL;
-
ao_cmd_register(&ao_adc_cmds[0]);
}
ao_cmd_register(&ao_adc_cmds[0]);
}
cfgr |= (AO_RCC_CFGR_PPRE2_DIV << STM_RCC_CFGR_PPRE2);
stm_rcc.cfgr = cfgr;
cfgr |= (AO_RCC_CFGR_PPRE2_DIV << STM_RCC_CFGR_PPRE2);
stm_rcc.cfgr = cfgr;
+ /* ADC Prescaler */
+ cfgr = stm_rcc.cfgr;
+ cfgr &= ~(STM_RCC_CFGR_ADCPRE_MASK << STM_RCC_CFGR_ADCPRE);
+ cfgr |= (AO_RCC_CFGR_ADCPRE << STM_RCC_CFGR_ADCPRE);
+ stm_rcc.cfgr = cfgr;
+
/* Disable the PLL */
stm_rcc.cr &= ~(1UL << STM_RCC_CR_PLLON);
while (stm_rcc.cr & (1UL << STM_RCC_CR_PLLRDY))
/* Disable the PLL */
stm_rcc.cr &= ~(1UL << STM_RCC_CR_PLLON);
while (stm_rcc.cr & (1UL << STM_RCC_CR_PLLRDY))
stm_rcc.csr |= (1 << STM_RCC_CSR_RMVF);
stm_rcc.csr |= (1 << STM_RCC_CSR_RMVF);
+ /* Release PB3, PA15 and PB4 from JTAG use */
+ stm_afio.mapr = (stm_afio.mapr &
+ ~(STM_AFIO_MAPR_SWJ_CFG_MASK << STM_AFIO_MAPR_SWJ_CFG)) |
+ STM_AFIO_MAPR_SWJ_CFG_SW_DP << STM_AFIO_MAPR_SWJ_CFG;
+
#if DEBUG_THE_CLOCK
/* Output SYSCLK on PA8 for measurments */
#if DEBUG_THE_CLOCK
/* Output SYSCLK on PA8 for measurments */
#define STM_RCC_CFGR_ADCPRE_4 1
#define STM_RCC_CFGR_ADCPRE_6 2
#define STM_RCC_CFGR_ADCPRE_8 3
#define STM_RCC_CFGR_ADCPRE_4 1
#define STM_RCC_CFGR_ADCPRE_6 2
#define STM_RCC_CFGR_ADCPRE_8 3
+#define STM_RCC_CFGR_ADCPRE_MASK 3UL
#define STM_RCC_CFGR_PPRE2 (11)
#define STM_RCC_CFGR_PPRE2_DIV_1 0
#define STM_RCC_CFGR_PPRE2 (11)
#define STM_RCC_CFGR_PPRE2_DIV_1 0
#define stm_afio (*((struct stm_afio *) 0x40010000))
#define stm_afio (*((struct stm_afio *) 0x40010000))
+#define STM_AFIO_MAPR_SWJ_CFG 24
+#define STM_AFIO_MAPR_SWJ_CFG_FULL_SWJ 0
+#define STM_AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJTRST 1
+#define STM_AFIO_MAPR_SWJ_CFG_SW_DP 2
+#define STM_AFIO_MAPR_SWJ_CFG_DISABLE 4
+#define STM_AFIO_MAPR_SWJ_CFG_MASK 7UL
#define STM_AFIO_MAPR_ADC2_ETRGREG_REMAP 20
#define STM_AFIO_MAPR_ADC2_ETRGINJ_REMAP 19
#define STM_AFIO_MAPR_ADC1_ETRGREG_REMAP 18
#define STM_AFIO_MAPR_ADC2_ETRGREG_REMAP 20
#define STM_AFIO_MAPR_ADC2_ETRGINJ_REMAP 19
#define STM_AFIO_MAPR_ADC1_ETRGREG_REMAP 18
-extern struct stm_adc stm_adc;
+extern struct stm_adc stm_adc1;
-#define stm_adc (*((struct stm_adc *) 0x40012400))
+//#define stm_adc1 (*((struct stm_adc *) 0x40012400))
#define STM_ADC_SQ_TEMP 16
#define STM_ADC_SQ_V_REF 17
#define STM_ADC_SQ_TEMP 16
#define STM_ADC_SQ_V_REF 17
#define STM_ADC_CR1_AWDCH_MASK 0x1fUL
#define STM_ADC_CR2_TSVREF 23
#define STM_ADC_CR1_AWDCH_MASK 0x1fUL
#define STM_ADC_CR2_TSVREF 23
-#define STM_ADC_CR2_SWSTART 21
+#define STM_ADC_CR2_SWSTART 22
#define STM_ADC_CR2_JWSTART 21
#define STM_ADC_CR2_EXTTRIG 20
#define STM_ADC_CR2_EXTSEL 17
#define STM_ADC_CR2_JWSTART 21
#define STM_ADC_CR2_EXTTRIG 20
#define STM_ADC_CR2_EXTSEL 17