projects / fw / openocd / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 5b053ff) | patch
tcl/target: Add Renesas RZ/A1H target
authorMarek Vasut <marek.vasut@gmail.com>
Fri, 5 Oct 2018 20:48:04 +0000 (22:48 +0200)
committerMatthias Welwarsky <matthias@welwarsky.de>
Mon, 20 May 2019 10:16:54 +0000 (11:16 +0100)
commit82e3a0e7cfa596e1b33e924036c82ab652b51619
tree7b3e245e1e3923ea21204128b5b05698a1664d7ctree | snapshot
parent5b053ffd438714bbc0b002aaa5f0f0634a0f3fe2commit | diff
tcl/target: Add Renesas RZ/A1H target

Add configuration for the Renesas RZ/A1H target.
This is an SoC with one Cortex A9 ARMv7a core and
up to 10 MiB of on-SoC SRAM.

Change-Id: I20fd54b385fe1ba1cc325451c3fdfa3a835d4884
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/5141
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
tcl/target/renesas_r7s72100.cfg [new file with mode: 0644] blob
openocd with support for Altus Metrum targets