flash/nor/efm32: Use Cortex-M 'core_info' field

[fw/openocd] / src / target / nds32.h

diff --git a/src/target/nds32.h b/src/target/nds32.h
index 141dbf4cb9bd10c2497a58173df8ff0bddbef1b9..c447673431ed2b3e8d7e2b9846f8cec671a3b50d 100644 (file)
--- a/src/target/nds32.h
+++ b/src/target/nds32.h
@@ -82,7 +82,7 @@ enum nds32_syscall_id {
        NDS32_SYSCALL_ERRNO = 6001,
 };
 
-#define NDS32_COMMON_MAGIC (int)0xADE5ADE5
+#define NDS32_COMMON_MAGIC 0xADE5ADE5U
 
 struct nds32_edm {
 
@@ -217,7 +217,7 @@ struct nds32_misc_config {
        bool div_instruction;
        bool mac_instruction;
        int audio_isa;
-       bool L2_cache;
+       bool l2_cache;
        bool reduce_register;
        bool addr_24;
        bool interruption_level;
@@ -235,7 +235,7 @@ struct nds32_misc_config {
  * Represents a generic Andes core.
  */
 struct nds32 {
-       int common_magic;
+       uint32_t common_magic;
        struct reg_cache *core_cache;
 
        /** Handle for the debug module. */
@@ -431,26 +431,26 @@ extern int nds32_profiling(struct target *target, uint32_t *samples,
 /** Convert target handle to generic Andes target state handle. */
 static inline struct nds32 *target_to_nds32(struct target *target)
 {
-       assert(target != NULL);
+       assert(target);
        return target->arch_info;
 }
 
 /** */
 static inline struct aice_port_s *target_to_aice(struct target *target)
 {
-       assert(target != NULL);
+       assert(target);
        return target->tap->priv;
 }
 
 static inline bool is_nds32(struct nds32 *nds32)
 {
-       assert(nds32 != NULL);
+       assert(nds32);
        return nds32->common_magic == NDS32_COMMON_MAGIC;
 }
 
 static inline bool nds32_reach_max_interrupt_level(struct nds32 *nds32)
 {
-       assert(nds32 != NULL);
+       assert(nds32);
        return nds32->max_interrupt_level == nds32->current_interrupt_level;
 }