target/register: Minor code cleanup

[fw/openocd] / src / target / feroceon.c

diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index ee0bafd2466eefc77d9c6eef17537f257345e492..1d1351bbc6442ac61efe1acc9e304a9000f3090e 100644 (file)
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -16,9 +16,7 @@
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
 /*
@@ -39,7 +37,7 @@
  * - asserting DBGRQ doesn't work if target is looping on the undef vector
  *
  * - the EICE version signature in the COMMS_CTL reg is next to the flow bits
- *   not at the top, and rather meaningless due to existing discrepencies
+ *   not at the top, and rather meaningless due to existing discrepancies
  *
  * - the DCC channel is half duplex (only one FIFO for both directions) with
  *   seemingly no proper flow control.
@@ -64,6 +62,13 @@ static int feroceon_assert_reset(struct target *target)
        struct arm7_9_common *arm7_9 = arm->arch_info;
        int ud = arm7_9->use_dbgrq;
 
+       /* TODO: apply hw reset signal in not examined state */
+       if (!(target_was_examined(target))) {
+               LOG_WARNING("Reset is not asserted because the target is not examined.");
+               LOG_WARNING("Use a reset button or power cycle the target.");
+               return ERROR_TARGET_NOT_EXAMINED;
+       }
+
        arm7_9->use_dbgrq = 0;
        if (target->reset_halt)
                arm7_9_halt(target);
@@ -88,7 +93,7 @@ static int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
        if (retval != ERROR_OK)
                return retval;
 
-       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+       retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
        if (retval != ERROR_OK)
                return retval;
 
@@ -455,7 +460,7 @@ static int feroceon_examine_debug_reason(struct target *target)
 }
 
 static int feroceon_bulk_write_memory(struct target *target,
-               uint32_t address, uint32_t count, const uint8_t *buffer)
+               target_addr_t address, uint32_t count, const uint8_t *buffer)
 {
        int retval;
        struct arm *arm = target->arch_info;
@@ -527,8 +532,8 @@ static int feroceon_bulk_write_memory(struct target *target,
 
        /* set up target address in r0 */
        buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, address);
-       arm->core_cache->reg_list[0].valid = 1;
-       arm->core_cache->reg_list[0].dirty = 1;
+       arm->core_cache->reg_list[0].valid = true;
+       arm->core_cache->reg_list[0].dirty = true;
        arm->core_state = ARM_STATE_ARM;
 
        embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0);
@@ -560,7 +565,7 @@ static int feroceon_bulk_write_memory(struct target *target,
                        buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32);
                if (endaddress != address + count*4) {
                        LOG_ERROR("DCC write failed,"
-                               " expected end address 0x%08" PRIx32
+                               " expected end address 0x%08" TARGET_PRIxADDR
                                " got 0x%0" PRIx32 "",
                                address + count*4, endaddress);
                        retval = ERROR_FAIL;
@@ -570,12 +575,12 @@ static int feroceon_bulk_write_memory(struct target *target,
        /* restore target state */
        for (i = 0; i <= 5; i++) {
                buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, save[i]);
-               arm->core_cache->reg_list[i].valid = 1;
-               arm->core_cache->reg_list[i].dirty = 1;
+               arm->core_cache->reg_list[i].valid = true;
+               arm->core_cache->reg_list[i].dirty = true;
        }
        buf_set_u32(arm->pc->value, 0, 32, save[i]);
-       arm->pc->valid = 1;
-       arm->pc->dirty = 1;
+       arm->pc->valid = true;
+       arm->pc->dirty = true;
        arm->core_state = core_state;
 
        return retval;
@@ -588,6 +593,11 @@ static int feroceon_init_target(struct command_context *cmd_ctx,
        return ERROR_OK;
 }
 
+static void feroceon_deinit_target(struct target *target)
+{
+       arm9tdmi_deinit_target(target);
+}
+
 static void feroceon_common_setup(struct target *target)
 {
        struct arm *arm = target->arch_info;
@@ -705,6 +715,7 @@ struct target_type feroceon_target = {
        .deassert_reset = arm7_9_deassert_reset,
        .soft_reset_halt = arm926ejs_soft_reset_halt,
 
+       .get_gdb_arch = arm_get_gdb_arch,
        .get_gdb_reg_list = arm_get_gdb_reg_list,
 
        .read_memory = arm7_9_read_memory,
@@ -723,6 +734,7 @@ struct target_type feroceon_target = {
        .commands = arm926ejs_command_handlers,
        .target_create = feroceon_target_create,
        .init_target = feroceon_init_target,
+       .deinit_target = feroceon_deinit_target,
        .examine = feroceon_examine,
 };
 
@@ -742,6 +754,7 @@ struct target_type dragonite_target = {
        .deassert_reset = arm7_9_deassert_reset,
        .soft_reset_halt = arm7_9_soft_reset_halt,
 
+       .get_gdb_arch = arm_get_gdb_arch,
        .get_gdb_reg_list = arm_get_gdb_reg_list,
 
        .read_memory = arm7_9_read_memory,