target/cortex_m: minor refactoring in cortex_m_store_core_reg_u32()

[fw/openocd] / src / target / cortex_m.c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 82d5eff80055c7a5ccd5b54a15d452436454a8a9..7125e9e8309f41873a81dbe8b2a05fecbfa6a56e 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -183,6 +183,7 @@ static int cortex_m_load_core_reg_u32(struct target *target,
                cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr);
                if (cortex_m->dcb_dhcsr & S_REGRDY)
                        break;
+               cortex_m->slow_register_read = true; /* Polling (still) needed. */
                if (timeval_ms() > then + DHCSR_S_REGRDY_TIMEOUT) {
                        LOG_ERROR("Timeout waiting for DCRDR transfer ready");
                        return ERROR_TIMEOUT_REACHED;
@@ -204,9 +205,14 @@ static int cortex_m_load_core_reg_u32(struct target *target,
 
 static int cortex_m_slow_read_all_regs(struct target *target)
 {
+       struct cortex_m_common *cortex_m = target_to_cm(target);
        struct armv7m_common *armv7m = target_to_armv7m(target);
        const unsigned int num_regs = armv7m->arm.core_cache->num_regs;
 
+       /* Opportunistically restore fast read, it'll revert to slow
+        * if any register needed polling in cortex_m_load_core_reg_u32(). */
+       cortex_m->slow_register_read = false;
+
        for (unsigned int reg_id = 0; reg_id < num_regs; reg_id++) {
                struct reg *r = &armv7m->arm.core_cache->reg_list[reg_id];
                if (r->exist) {
@@ -215,6 +221,10 @@ static int cortex_m_slow_read_all_regs(struct target *target)
                                return retval;
                }
        }
+
+       if (!cortex_m->slow_register_read)
+               LOG_DEBUG("Switching back to fast register reads");
+
        return ERROR_OK;
 }
 
@@ -387,11 +397,9 @@ static int cortex_m_store_core_reg_u32(struct target *target,
        /* check if value is written into register */
        then = timeval_ms();
        while (1) {
-               retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
-                                                                               &cortex_m->dcb_dhcsr);
+               retval = cortex_m_read_dhcsr_atomic_sticky(target);
                if (retval != ERROR_OK)
                        return retval;
-               cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr);
                if (cortex_m->dcb_dhcsr & S_REGRDY)
                        break;
                if (timeval_ms() > then + DHCSR_S_REGRDY_TIMEOUT) {
@@ -2282,7 +2290,6 @@ int cortex_m_examine(struct target *target)
                        armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
                }
 
-               /* Leave (only) generic DAP stuff for debugport_init(); */
                armv7m->debug_ap->memaccess_tck = 8;
 
                retval = mem_ap_init(armv7m->debug_ap);
@@ -2579,7 +2586,7 @@ static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
 static int cortex_m_verify_pointer(struct command_invocation *cmd,
        struct cortex_m_common *cm)
 {
-       if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
+       if (!is_cortex_m_with_dap_access(cm)) {
                command_print(cmd, "target is not a Cortex-M");
                return ERROR_TARGET_INVALID;
        }