aarch64: handle semihosting in aarch32 state

[fw/openocd] / src / target / armv7m.h

diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 8cd4df36ffc4960613175bcc868fc2bcad004db4..db6f8bc5246c1ce8ce9f55c57a7ac61d97df0778 100644 (file)
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -128,45 +128,21 @@ enum {
        ARMV7M_PSP = ARMV7M_REGSEL_PSP,
 
        /* following indices are arbitrary, do not match DCRSR.REGSEL selectors */
+
+       /* working register for packing/unpacking special regs, hidden from gdb */
+       ARMV7M_PMSK_BPRI_FLTMSK_CTRL,
+
+       /* WARNING: If you use armv7m_write_core_reg() on one of 4 following
+        * special registers, the new data go to ARMV7M_PMSK_BPRI_FLTMSK_CTRL
+        * cache only and are not flushed to CPU HW register.
+        * To trigger write to CPU HW register, add
+        *              armv7m_write_core_reg(,,ARMV7M_PMSK_BPRI_FLTMSK_CTRL,);
+        */
        ARMV7M_PRIMASK,
        ARMV7M_BASEPRI,
        ARMV7M_FAULTMASK,
        ARMV7M_CONTROL,
 
-       /* 32bit Floating-point registers */
-       ARMV7M_S0,
-       ARMV7M_S1,
-       ARMV7M_S2,
-       ARMV7M_S3,
-       ARMV7M_S4,
-       ARMV7M_S5,
-       ARMV7M_S6,
-       ARMV7M_S7,
-       ARMV7M_S8,
-       ARMV7M_S9,
-       ARMV7M_S10,
-       ARMV7M_S11,
-       ARMV7M_S12,
-       ARMV7M_S13,
-       ARMV7M_S14,
-       ARMV7M_S15,
-       ARMV7M_S16,
-       ARMV7M_S17,
-       ARMV7M_S18,
-       ARMV7M_S19,
-       ARMV7M_S20,
-       ARMV7M_S21,
-       ARMV7M_S22,
-       ARMV7M_S23,
-       ARMV7M_S24,
-       ARMV7M_S25,
-       ARMV7M_S26,
-       ARMV7M_S27,
-       ARMV7M_S28,
-       ARMV7M_S29,
-       ARMV7M_S30,
-       ARMV7M_S31,
-
        /* 64bit Floating-point registers */
        ARMV7M_D0,
        ARMV7M_D1,
@@ -185,10 +161,8 @@ enum {
        ARMV7M_D14,
        ARMV7M_D15,
 
-       /* Floating-point status registers */
-       ARMV7M_FPSID,
+       /* Floating-point status register */
        ARMV7M_FPSCR,
-       ARMV7M_FPEXC,
 
        ARMV7M_LAST_REG,
 };