#include "config.h"
#endif
-#include "arm11.h"
+#include "etm.h"
#include "breakpoints.h"
#include "arm11_dbgtap.h"
-#include "armv4_5.h"
#include "arm_simulator.h"
#include "time_support.h"
#include "target_type.h"
#include "algorithm.h"
+#include "register.h"
#if 0
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
-#if 0
-#define FNC_INFO LOG_DEBUG("-")
-#else
-#define FNC_INFO
-#endif
-
-#if 1
-#define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
-#else
-#define FNC_INFO_NOTIMPLEMENTED
-#endif
-
static bool arm11_config_memwrite_burst = true;
static bool arm11_config_memwrite_error_fatal = true;
static uint32_t arm11_vcr = 0;
static bool arm11_config_step_irq_enable = false;
static bool arm11_config_hardware_step = false;
-static int arm11_regs_arch_type = -1;
-
enum arm11_regtype
{
- ARM11_REGISTER_CORE,
- ARM11_REGISTER_CPSR,
-
- ARM11_REGISTER_FX,
- ARM11_REGISTER_FPS,
-
- ARM11_REGISTER_FIQ,
- ARM11_REGISTER_SVC,
- ARM11_REGISTER_ABT,
- ARM11_REGISTER_IRQ,
- ARM11_REGISTER_UND,
- ARM11_REGISTER_MON,
-
- ARM11_REGISTER_SPSR_FIQ,
- ARM11_REGISTER_SPSR_SVC,
- ARM11_REGISTER_SPSR_ABT,
- ARM11_REGISTER_SPSR_IRQ,
- ARM11_REGISTER_SPSR_UND,
- ARM11_REGISTER_SPSR_MON,
-
/* debug regs */
ARM11_REGISTER_DSCR,
ARM11_REGISTER_WDTR,
/* update arm11_regcache_ids when changing this */
static const struct arm11_reg_defs arm11_reg_defs[] =
{
- {"r0", 0, 0, ARM11_REGISTER_CORE},
- {"r1", 1, 1, ARM11_REGISTER_CORE},
- {"r2", 2, 2, ARM11_REGISTER_CORE},
- {"r3", 3, 3, ARM11_REGISTER_CORE},
- {"r4", 4, 4, ARM11_REGISTER_CORE},
- {"r5", 5, 5, ARM11_REGISTER_CORE},
- {"r6", 6, 6, ARM11_REGISTER_CORE},
- {"r7", 7, 7, ARM11_REGISTER_CORE},
- {"r8", 8, 8, ARM11_REGISTER_CORE},
- {"r9", 9, 9, ARM11_REGISTER_CORE},
- {"r10", 10, 10, ARM11_REGISTER_CORE},
- {"r11", 11, 11, ARM11_REGISTER_CORE},
- {"r12", 12, 12, ARM11_REGISTER_CORE},
- {"sp", 13, 13, ARM11_REGISTER_CORE},
- {"lr", 14, 14, ARM11_REGISTER_CORE},
- {"pc", 15, 15, ARM11_REGISTER_CORE},
-
-#if ARM11_REGCACHE_FREGS
- {"f0", 0, 16, ARM11_REGISTER_FX},
- {"f1", 1, 17, ARM11_REGISTER_FX},
- {"f2", 2, 18, ARM11_REGISTER_FX},
- {"f3", 3, 19, ARM11_REGISTER_FX},
- {"f4", 4, 20, ARM11_REGISTER_FX},
- {"f5", 5, 21, ARM11_REGISTER_FX},
- {"f6", 6, 22, ARM11_REGISTER_FX},
- {"f7", 7, 23, ARM11_REGISTER_FX},
- {"fps", 0, 24, ARM11_REGISTER_FPS},
-#endif
-
- {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
-
-#if ARM11_REGCACHE_MODEREGS
- {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
- {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
- {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
- {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
- {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
- {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
- {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
- {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
-
- {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
- {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
- {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
-
- {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
- {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
- {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
-
- {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
- {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
- {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
-
- {"r13_und", 13, -1, ARM11_REGISTER_UND},
- {"r14_und", 14, -1, ARM11_REGISTER_UND},
- {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
-
- /* ARM1176 only */
- {"r13_mon", 13, -1, ARM11_REGISTER_MON},
- {"r14_mon", 14, -1, ARM11_REGISTER_MON},
- {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
-#endif
-
/* Debug Registers */
{"dscr", 0, -1, ARM11_REGISTER_DSCR},
{"wdtr", 0, -1, ARM11_REGISTER_WDTR},
enum arm11_regcache_ids
{
- ARM11_RC_R0,
- ARM11_RC_RX = ARM11_RC_R0,
-
- ARM11_RC_R1,
- ARM11_RC_R2,
- ARM11_RC_R3,
- ARM11_RC_R4,
- ARM11_RC_R5,
- ARM11_RC_R6,
- ARM11_RC_R7,
- ARM11_RC_R8,
- ARM11_RC_R9,
- ARM11_RC_R10,
- ARM11_RC_R11,
- ARM11_RC_R12,
- ARM11_RC_R13,
- ARM11_RC_SP = ARM11_RC_R13,
- ARM11_RC_R14,
- ARM11_RC_LR = ARM11_RC_R14,
- ARM11_RC_R15,
- ARM11_RC_PC = ARM11_RC_R15,
-
-#if ARM11_REGCACHE_FREGS
- ARM11_RC_F0,
- ARM11_RC_FX = ARM11_RC_F0,
- ARM11_RC_F1,
- ARM11_RC_F2,
- ARM11_RC_F3,
- ARM11_RC_F4,
- ARM11_RC_F5,
- ARM11_RC_F6,
- ARM11_RC_F7,
- ARM11_RC_FPS,
-#endif
-
- ARM11_RC_CPSR,
-
-#if ARM11_REGCACHE_MODEREGS
- ARM11_RC_R8_FIQ,
- ARM11_RC_R9_FIQ,
- ARM11_RC_R10_FIQ,
- ARM11_RC_R11_FIQ,
- ARM11_RC_R12_FIQ,
- ARM11_RC_R13_FIQ,
- ARM11_RC_R14_FIQ,
- ARM11_RC_SPSR_FIQ,
-
- ARM11_RC_R13_SVC,
- ARM11_RC_R14_SVC,
- ARM11_RC_SPSR_SVC,
-
- ARM11_RC_R13_ABT,
- ARM11_RC_R14_ABT,
- ARM11_RC_SPSR_ABT,
-
- ARM11_RC_R13_IRQ,
- ARM11_RC_R14_IRQ,
- ARM11_RC_SPSR_IRQ,
-
- ARM11_RC_R13_UND,
- ARM11_RC_R14_UND,
- ARM11_RC_SPSR_UND,
-
- ARM11_RC_R13_MON,
- ARM11_RC_R14_MON,
- ARM11_RC_SPSR_MON,
-#endif
-
ARM11_RC_DSCR,
ARM11_RC_WDTR,
ARM11_RC_RDTR,
ARM11_RC_MAX,
};
-#define ARM11_GDB_REGISTER_COUNT 26
-
-/* FIXME these are *identical* to the ARMv4_5 dummies ... except
- * for their names, and being static vs global, and having different
- * addresses. Ditto ARMv7a and ARMv7m dummies.
- */
-
-static uint8_t arm11_gdb_dummy_fp_value[12];
-
-static struct reg arm11_gdb_dummy_fp_reg =
-{
- .name = "GDB dummy floating-point register",
- .value = arm11_gdb_dummy_fp_value,
- .dirty = 0,
- .valid = 1,
- .size = 96,
- .arch_info = NULL,
- .arch_type = 0,
-};
-
-static uint8_t arm11_gdb_dummy_fps_value[4];
-
-static struct reg arm11_gdb_dummy_fps_reg =
-{
- .name = "GDB dummy floating-point status register",
- .value = arm11_gdb_dummy_fps_value,
- .dirty = 0,
- .valid = 1,
- .size = 32,
- .arch_info = NULL,
- .arch_type = 0,
-};
-
-
static int arm11_on_enter_debug_state(struct arm11_common *arm11);
static int arm11_step(struct target *target, int current,
uint32_t address, int handle_breakpoints);
static int arm11_set_reg(struct reg *reg, uint8_t *buf);
static int arm11_get_reg(struct reg *reg);
-static void arm11_record_register_history(struct arm11_common * arm11);
-static void arm11_dump_reg_changes(struct arm11_common * arm11);
-
/** Check and if necessary take control of the system
*
*/
static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr)
{
- FNC_INFO;
-
uint32_t dscr_local_tmp_copy;
if (!dscr)
static int arm11_on_enter_debug_state(struct arm11_common *arm11)
{
int retval;
- FNC_INFO;
- for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
+ /* REVISIT entire cache should already be invalid !!! */
+ register_cache_invalidate(arm11->arm.core_cache);
+
+ for (size_t i = 0; i < ARRAY_SIZE(arm11->reg_values); i++)
{
arm11->reg_list[i].valid = 1;
arm11->reg_list[i].dirty = 0;
}
+ /* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */
+
/* Save DSCR */
CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
else
{
}
- /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
- /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
- ARM1136 seems to require this to issue ITR's as well */
-
+ /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
+ *
+ * ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode",
+ * but not to issue ITRs. ARM1136 seems to require this to issue
+ * ITR's as well...
+ */
uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
/* this executes JTAG queue: */
}
#endif
+ /* Save registers.
+ *
+ * NOTE: ARM1136 TRM suggests saving just R0 here now, then
+ * CPSR and PC after the rDTR stuff. We do it all at once.
+ */
+ retval = arm_dpm_read_current_registers(&arm11->dpm);
+ if (retval != ERROR_OK)
+ LOG_ERROR("DPM REG READ -- fail %d", retval);
+
retval = arm11_run_instr_data_prepare(arm11);
if (retval != ERROR_OK)
return retval;
- /* save r0 - r14 */
-
- /** \todo TODO: handle other mode registers */
-
- for (size_t i = 0; i < 15; i++)
- {
- /* MCR p14,0,R?,c0,c5,0 */
- retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
- if (retval != ERROR_OK)
- return retval;
- }
-
- /* save rDTR */
+ /* maybe save rDTR */
/* check rDTRfull in DSCR */
arm11->reg_list[ARM11_RC_RDTR].valid = 0;
}
- /* save CPSR */
-
- /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
- retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
- if (retval != ERROR_OK)
- return retval;
-
- /* save PC */
-
- /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
- retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
- if (retval != ERROR_OK)
- return retval;
-
- /* adjust PC depending on ARM state */
-
- if (R(CPSR) & ARM11_CPSR_J) /* Java state */
- {
- arm11->reg_values[ARM11_RC_PC] -= 0;
- }
- else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
- {
- arm11->reg_values[ARM11_RC_PC] -= 4;
- }
- else /* ARM state */
- {
- arm11->reg_values[ARM11_RC_PC] -= 8;
- }
+ /* REVISIT Now that we've saved core state, there's may also
+ * be MMU and cache state to care about ...
+ */
if (arm11->simulate_reset_on_next_halt)
{
if (retval != ERROR_OK)
return retval;
- arm11_dump_reg_changes(arm11);
-
return ERROR_OK;
}
-void arm11_dump_reg_changes(struct arm11_common * arm11)
-{
-
- if (!(debug_level >= LOG_LVL_DEBUG))
- {
- return;
- }
-
- for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
- {
- if (!arm11->reg_list[i].valid)
- {
- if (arm11->reg_history[i].valid)
- LOG_DEBUG("%8s INVALID (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
- }
- else
- {
- if (arm11->reg_history[i].valid)
- {
- if (arm11->reg_history[i].value != arm11->reg_values[i])
- LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
- }
- else
- {
- LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
- }
- }
- }
-}
-
/** Restore processor state
*
* This is called in preparation for the RESTART function.
*/
static int arm11_leave_debug_state(struct arm11_common *arm11)
{
- FNC_INFO;
int retval;
- retval = arm11_run_instr_data_prepare(arm11);
- if (retval != ERROR_OK)
- return retval;
-
- /** \todo TODO: handle other mode registers */
-
- /* restore R1 - R14 */
+ /* See e.g. ARM1136 TRM, "14.8.5 Leaving Debug state" */
- for (size_t i = 1; i < 15; i++)
- {
- if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
- continue;
-
- /* MRC p14,0,r?,c0,c5,0 */
- arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
-
- // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
- }
+ /* NOTE: the ARM1136 TRM suggests restoring all registers
+ * except R0/PC/CPSR right now. Instead, we do them all
+ * at once, just a bit later on.
+ */
- retval = arm11_run_instr_data_finish(arm11);
- if (retval != ERROR_OK)
- return retval;
+ /* REVISIT once we start caring about MMU and cache state,
+ * address it here ...
+ */
/* spec says clear wDTR and rDTR; we assume they are clear as
otherwise our programming would be sloppy */
}
}
- retval = arm11_run_instr_data_prepare(arm11);
- if (retval != ERROR_OK)
- return retval;
-
- /* restore original wDTR */
-
+ /* maybe restore original wDTR */
if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
{
+ retval = arm11_run_instr_data_prepare(arm11);
+ if (retval != ERROR_OK)
+ return retval;
+
/* MCR p14,0,R0,c0,c5,0 */
retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
if (retval != ERROR_OK)
return retval;
- }
-
- /* restore CPSR */
-
- /* MSR CPSR,R0*/
- retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
- if (retval != ERROR_OK)
- return retval;
-
-
- /* restore PC */
-
- /* MOV PC,R0 */
- retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
- if (retval != ERROR_OK)
- return retval;
+ retval = arm11_run_instr_data_finish(arm11);
+ if (retval != ERROR_OK)
+ return retval;
+ }
- /* restore R0 */
+ /* restore CPSR, PC, and R0 ... after flushing any modified
+ * registers.
+ */
+ retval = arm_dpm_write_dirty_registers(&arm11->dpm);
- /* MRC p14,0,r0,c0,c5,0 */
- arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
-
- retval = arm11_run_instr_data_finish(arm11);
- if (retval != ERROR_OK)
- return retval;
+ register_cache_invalidate(arm11->arm.core_cache);
/* restore DSCR */
arm11_write_DSCR(arm11, R(DSCR));
- /* restore rDTR */
+ /* maybe restore rDTR */
if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
{
arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
- arm11_record_register_history(arm11);
+ /* now processor is ready to RESTART */
return ERROR_OK;
}
-static void arm11_record_register_history(struct arm11_common *arm11)
-{
- for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
- {
- arm11->reg_history[i].value = arm11->reg_values[i];
- arm11->reg_history[i].valid = arm11->reg_list[i].valid;
-
- arm11->reg_list[i].valid = 0;
- arm11->reg_list[i].dirty = 0;
- }
-}
-
-
/* poll current target status */
static int arm11_poll(struct target *target)
{
- FNC_INFO;
int retval;
struct arm11_common *arm11 = target_to_arm11(target);
uint32_t dscr;
/* architecture specific status reply */
static int arm11_arch_state(struct target *target)
{
- struct arm11_common *arm11 = target_to_arm11(target);
+ int retval;
- LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
- Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
- R(CPSR),
- R(PC));
+ retval = armv4_5_arch_state(target);
- return ERROR_OK;
+ /* REVISIT also display ARM11-specific MMU and cache status ... */
+
+ return retval;
}
/* target request support */
static int arm11_target_request_data(struct target *target,
uint32_t size, uint8_t *buffer)
{
- FNC_INFO_NOTIMPLEMENTED;
+ LOG_WARNING("Not implemented: %s", __func__);
- return ERROR_OK;
+ return ERROR_FAIL;
}
/* target execution control */
static int arm11_halt(struct target *target)
{
- FNC_INFO;
struct arm11_common *arm11 = target_to_arm11(target);
LOG_DEBUG("target->state: %s",
return ERROR_OK;
}
+static uint32_t
+arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address)
+{
+ void *value = arm11->arm.core_cache->reg_list[15].value;
+
+ if (!current)
+ buf_set_u32(value, 0, 32, address);
+ else
+ address = buf_get_u32(value, 0, 32);
+
+ return address;
+}
+
static int arm11_resume(struct target *target, int current,
uint32_t address, int handle_breakpoints, int debug_execution)
{
- FNC_INFO;
-
// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
// current, address, handle_breakpoints, debug_execution);
return ERROR_TARGET_NOT_HALTED;
}
- if (!current)
- R(PC) = address;
+ address = arm11_nextpc(arm11, current, address);
- LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
+ LOG_DEBUG("RESUME PC %08" PRIx32 "%s", address, !current ? "!" : "");
/* clear breakpoints/watchpoints and VCR*/
arm11_sc7_clear_vbw(arm11);
- /* Set up breakpoints */
if (!debug_execution)
+ target_free_all_working_areas(target);
+
+ /* Set up breakpoints */
+ if (handle_breakpoints)
{
/* check if one matches PC and step over it if necessary */
for (bp = target->breakpoints; bp; bp = bp->next)
{
- if (bp->address == R(PC))
+ if (bp->address == address)
{
LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
arm11_step(target, 1, 0, 0);
/* set all breakpoints */
- size_t brp_num = 0;
+ unsigned brp_num = 0;
for (bp = target->breakpoints; bp; bp = bp->next)
{
brp[1].address = ARM11_SC7_BCR0 + brp_num;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
- arm11_sc7_run(arm11, brp, asizeof(brp));
+ arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp));
- LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
+ LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num,
+ bp->address);
brp_num++;
}
return ERROR_OK;
}
-
-static int armv4_5_to_arm11(int reg)
-{
- if (reg < 16)
- return reg;
- switch (reg)
- {
- case ARMV4_5_CPSR:
- return ARM11_RC_CPSR;
- case 16:
- /* FIX!!! handle thumb better! */
- return ARM11_RC_CPSR;
- default:
- LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
- exit(-1);
- }
-}
-
-
-static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
-{
- struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
-
- reg=armv4_5_to_arm11(reg);
-
- return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
-}
-
-static void arm11_sim_set_reg(struct arm_sim_interface *sim,
- int reg, uint32_t value)
-{
- struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
-
- reg=armv4_5_to_arm11(reg);
-
- buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
-}
-
-static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim,
- int pos, int bits)
-{
- struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
-
- return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
-}
-
-static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
-{
-// struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
-
- /* FIX!!!! we should implement thumb for arm11 */
- return ARMV4_5_STATE_ARM;
-}
-
-static void arm11_sim_set_state(struct arm_sim_interface *sim,
- enum armv4_5_state mode)
-{
-// struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
-
- /* FIX!!!! we should implement thumb for arm11 */
- LOG_ERROR("Not implemetned!");
-}
-
-
-static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
-{
- //struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
-
- /* FIX!!!! we should implement something that returns the current mode here!!! */
- return ARMV4_5_MODE_USR;
-}
-
-static int arm11_simulate_step(struct target *target, uint32_t *dry_run_pc)
-{
- struct arm_sim_interface sim;
-
- sim.user_data=target->arch_info;
- sim.get_reg=&arm11_sim_get_reg;
- sim.set_reg=&arm11_sim_set_reg;
- sim.get_reg_mode=&arm11_sim_get_reg;
- sim.set_reg_mode=&arm11_sim_set_reg;
- sim.get_cpsr=&arm11_sim_get_cpsr;
- sim.get_mode=&arm11_sim_get_mode;
- sim.get_state=&arm11_sim_get_state;
- sim.set_state=&arm11_sim_set_state;
-
- return arm_simulate_step_core(target, dry_run_pc, &sim);
-
-}
-
static int arm11_step(struct target *target, int current,
uint32_t address, int handle_breakpoints)
{
- FNC_INFO;
-
LOG_DEBUG("target->state: %s",
target_state_name(target));
struct arm11_common *arm11 = target_to_arm11(target);
- if (!current)
- R(PC) = address;
+ address = arm11_nextpc(arm11, current, address);
- LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
+ LOG_DEBUG("STEP PC %08" PRIx32 "%s", address, !current ? "!" : "");
/** \todo TODO: Thumb not supported here */
uint32_t next_instruction;
- CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
+ CHECK_RETVAL(arm11_read_memory_word(arm11, address, &next_instruction));
/* skip over BKPT */
if ((next_instruction & 0xFFF00070) == 0xe1200070)
{
- R(PC) += 4;
- arm11->reg_list[ARM11_RC_PC].valid = 1;
- arm11->reg_list[ARM11_RC_PC].dirty = 0;
+ address = arm11_nextpc(arm11, 0, address + 4);
LOG_DEBUG("Skipping BKPT");
}
/* skip over Wait for interrupt / Standby */
/* mcr 15, 0, r?, cr7, cr0, {4} */
else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
{
- R(PC) += 4;
- arm11->reg_list[ARM11_RC_PC].valid = 1;
- arm11->reg_list[ARM11_RC_PC].dirty = 0;
+ address = arm11_nextpc(arm11, 0, address + 4);
LOG_DEBUG("Skipping WFI");
}
/* ignore B to self */
if (arm11_config_hardware_step)
{
- /* hardware single stepping be used if possible or is it better to
- * always use the same code path? Hardware single stepping is not supported
- * on all hardware
+ /* Hardware single stepping ("instruction address
+ * mismatch") is used if enabled. It's not quite
+ * exactly "run one instruction"; "branch to here"
+ * loops won't break, neither will some other cases,
+ * but it's probably the best default.
+ *
+ * Hardware single stepping isn't supported on v6
+ * debug modules. ARM1176 and v7 can support it...
+ *
+ * FIXME Thumb stepping likely needs to use 0x03
+ * or 0xc0 byte masks, not 0x0f.
*/
- brp[0].value = R(PC);
- brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
+ brp[0].value = address;
+ brp[1].value = 0x1 | (3 << 1) | (0x0F << 5)
+ | (0 << 14) | (0 << 16) | (0 << 20)
+ | (2 << 21);
} else
{
- /* sets a breakpoint on the next PC(calculated by simulation),
+ /* Sets a breakpoint on the next PC, as calculated
+ * by instruction set simulation.
+ *
+ * REVISIT stepping Thumb on ARM1156 requires Thumb2
+ * support from the simulator.
*/
uint32_t next_pc;
int retval;
- retval = arm11_simulate_step(target, &next_pc);
+
+ retval = arm_simulate_step(target, &next_pc);
if (retval != ERROR_OK)
return retval;
brp[0].value = next_pc;
- brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
+ brp[1].value = 0x1 | (3 << 1) | (0x0F << 5)
+ | (0 << 14) | (0 << 16) | (0 << 20)
+ | (0 << 21);
}
- CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
+ CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
/* resume */
static int arm11_assert_reset(struct target *target)
{
- FNC_INFO;
int retval;
struct arm11_common *arm11 = target_to_arm11(target);
static int arm11_soft_reset_halt(struct target *target)
{
- FNC_INFO_NOTIMPLEMENTED;
+ LOG_WARNING("Not implemented: %s", __func__);
- return ERROR_OK;
-}
-
-/* target register access for gdb */
-static int arm11_get_gdb_reg_list(struct target *target,
- struct reg **reg_list[], int *reg_list_size)
-{
- FNC_INFO;
- struct arm11_common *arm11 = target_to_arm11(target);
-
- *reg_list_size = ARM11_GDB_REGISTER_COUNT;
- *reg_list = malloc(sizeof(struct reg*) * ARM11_GDB_REGISTER_COUNT);
-
- for (size_t i = 16; i < 24; i++)
- {
- (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
- }
-
- (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
-
- for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
- {
- if (arm11_reg_defs[i].gdb_num == -1)
- continue;
-
- (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
- }
-
- return ERROR_OK;
+ return ERROR_FAIL;
}
/* target memory access
/** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
int retval;
- FNC_INFO;
-
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target was not halted");
switch (size)
{
case 1:
- /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
- arm11->reg_list[ARM11_RC_R1].dirty = 1;
+ arm11->arm.core_cache->reg_list[1].dirty = true;
for (size_t i = 0; i < count; i++)
{
case 2:
{
- arm11->reg_list[ARM11_RC_R1].dirty = 1;
+ arm11->arm.core_cache->reg_list[1].dirty = true;
for (size_t i = 0; i < count; i++)
{
bool arm11_config_memrw_no_increment)
{
int retval;
- FNC_INFO;
if (target->state != TARGET_HALTED)
{
{
case 1:
{
- arm11->reg_list[ARM11_RC_R1].dirty = 1;
+ arm11->arm.core_cache->reg_list[1].dirty = true;
for (size_t i = 0; i < count; i++)
{
case 2:
{
- arm11->reg_list[ARM11_RC_R1].dirty = 1;
+ arm11->arm.core_cache->reg_list[1].dirty = true;
for (size_t i = 0; i < count; i++)
{
static int arm11_bulk_write_memory(struct target *target,
uint32_t address, uint32_t count, uint8_t *buffer)
{
- FNC_INFO;
-
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target was not halted");
static int arm11_add_breakpoint(struct target *target,
struct breakpoint *breakpoint)
{
- FNC_INFO;
struct arm11_common *arm11 = target_to_arm11(target);
#if 0
static int arm11_remove_breakpoint(struct target *target,
struct breakpoint *breakpoint)
{
- FNC_INFO;
struct arm11_common *arm11 = target_to_arm11(target);
arm11->free_brps++;
static int arm11_add_watchpoint(struct target *target,
struct watchpoint *watchpoint)
{
- FNC_INFO_NOTIMPLEMENTED;
+ LOG_WARNING("Not implemented: %s", __func__);
- return ERROR_OK;
+ return ERROR_FAIL;
}
static int arm11_remove_watchpoint(struct target *target,
struct watchpoint *watchpoint)
{
- FNC_INFO_NOTIMPLEMENTED;
-
- return ERROR_OK;
-}
-
-// HACKHACKHACK - FIXME mode/state
-/* target algorithm support */
-static int arm11_run_algorithm(struct target *target,
- int num_mem_params, struct mem_param *mem_params,
- int num_reg_params, struct reg_param *reg_params,
- uint32_t entry_point, uint32_t exit_point,
- int timeout_ms, void *arch_info)
-{
- struct arm11_common *arm11 = target_to_arm11(target);
-// enum armv4_5_state core_state = arm11->core_state;
-// enum armv4_5_mode core_mode = arm11->core_mode;
- uint32_t context[16];
- uint32_t cpsr;
- int exit_breakpoint_size = 0;
- int retval = ERROR_OK;
- LOG_DEBUG("Running algorithm");
-
-
- if (target->state != TARGET_HALTED)
- {
- LOG_WARNING("target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
-
- // FIXME
-// if (armv4_5_mode_to_number(arm11->core_mode)==-1)
-// return ERROR_FAIL;
-
- // Save regs
- for (unsigned i = 0; i < 16; i++)
- {
- context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
- LOG_DEBUG("Save %u: 0x%" PRIx32 "", i, context[i]);
- }
-
- cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
- LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
-
- for (int i = 0; i < num_mem_params; i++)
- {
- target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
- }
-
- // Set register parameters
- for (int i = 0; i < num_reg_params; i++)
- {
- struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
- if (!reg)
- {
- LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
- exit(-1);
- }
-
- if (reg->size != reg_params[i].size)
- {
- LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
- exit(-1);
- }
- arm11_set_reg(reg,reg_params[i].value);
-// printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
- }
-
- exit_breakpoint_size = 4;
-
-/* arm11->core_state = arm11_algorithm_info->core_state;
- if (arm11->core_state == ARMV4_5_STATE_ARM)
- exit_breakpoint_size = 4;
- else if (arm11->core_state == ARMV4_5_STATE_THUMB)
- exit_breakpoint_size = 2;
- else
- {
- LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
- exit(-1);
- }
-*/
-
-
-/* arm11 at this point only supports ARM not THUMB mode
- however if this test needs to be reactivated the current state can be read back
- from CPSR */
-#if 0
- if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
- {
- LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
- buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
- arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
- arm11->reg_list[ARM11_RC_CPSR].valid = 1;
- }
-#endif
-
- if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
- {
- LOG_ERROR("can't add breakpoint to finish algorithm execution");
- retval = ERROR_TARGET_FAILURE;
- goto restore;
- }
-
- // no debug, otherwise breakpoint is not set
- CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
-
- CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
-
- if (target->state != TARGET_HALTED)
- {
- CHECK_RETVAL(target_halt(target));
-
- CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
-
- retval = ERROR_TARGET_TIMEOUT;
-
- goto del_breakpoint;
- }
-
- if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
- {
- LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
- buf_get_u32(arm11->reg_list[15].value, 0, 32));
- retval = ERROR_TARGET_TIMEOUT;
- goto del_breakpoint;
- }
-
- for (int i = 0; i < num_mem_params; i++)
- {
- if (mem_params[i].direction != PARAM_OUT)
- target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
- }
-
- for (int i = 0; i < num_reg_params; i++)
- {
- if (reg_params[i].direction != PARAM_OUT)
- {
- struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
- if (!reg)
- {
- LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
- exit(-1);
- }
+ LOG_WARNING("Not implemented: %s", __func__);
- if (reg->size != reg_params[i].size)
- {
- LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
- exit(-1);
- }
-
- buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
- }
- }
-
-del_breakpoint:
- breakpoint_remove(target, exit_point);
-
-restore:
- // Restore context
- for (size_t i = 0; i < 16; i++)
- {
- LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
- arm11->reg_list[i].name, context[i]);
- arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
- }
- LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
- arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
-
-// arm11->core_state = core_state;
-// arm11->core_mode = core_mode;
-
- return retval;
+ return ERROR_FAIL;
}
static int arm11_target_create(struct target *target, Jim_Interp *interp)
{
- FNC_INFO;
-
- NEW(struct arm11_common, arm11, 1);
-
- arm11->target = target;
+ struct arm11_common *arm11;
if (target->tap == NULL)
return ERROR_FAIL;
return ERROR_COMMAND_SYNTAX_ERROR;
}
+ arm11 = calloc(1, sizeof *arm11);
+ if (!arm11)
+ return ERROR_FAIL;
+
armv4_5_init_arch_info(target, &arm11->arm);
+ arm11->target = target;
+
arm11->jtag_info.tap = target->tap;
arm11->jtag_info.scann_size = 5;
arm11->jtag_info.scann_instr = ARM11_SCAN_N;
struct target *target)
{
/* Initialize anything we can set up without talking to the target */
+
+ /* REVISIT do we really want such a debug-registers-only cache?
+ * If we do, it should probably be handled purely by the DPM code,
+ * so it works identically on the v7a/v7r cores.
+ */
return arm11_build_reg_cache(target);
}
static int arm11_examine(struct target *target)
{
int retval;
-
- FNC_INFO;
+ char *type;
struct arm11_common *arm11 = target_to_arm11(target);
+ uint32_t didr, device_id;
+ uint8_t implementor;
+
+ /* FIXME split into do-first-time and do-every-time logic ... */
/* check IDCODE */
struct scan_field idcode_field;
- arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
+ arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
struct scan_field chain0_fields[2];
- arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
- arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
+ arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
+ arm11_setup_field(arm11, 8, NULL, &implementor, chain0_fields + 1);
- arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
CHECK_RETVAL(jtag_execute_queue());
- switch (arm11->device_id & 0x0FFFF000)
+ switch (device_id & 0x0FFFF000)
{
- case 0x07B36000: LOG_INFO("found ARM1136"); break;
- case 0x07B56000: LOG_INFO("found ARM1156"); break;
- case 0x07B76000: LOG_INFO("found ARM1176"); break;
+ case 0x07B36000:
+ type = "ARM1136";
+ break;
+ case 0x07B56000:
+ type = "ARM1156";
+ break;
+ case 0x07B76000:
+ arm11->arm.core_type = ARM_MODE_MON;
+ type = "ARM1176";
+ break;
default:
LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
return ERROR_FAIL;
}
+ LOG_INFO("found %s", type);
- arm11->debug_version = (arm11->didr >> 16) & 0x0F;
-
- if (arm11->debug_version != ARM11_DEBUG_V6 &&
- arm11->debug_version != ARM11_DEBUG_V61)
- {
- LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
+ /* unlikely this could ever fail, but ... */
+ switch ((didr >> 16) & 0x0F) {
+ case ARM11_DEBUG_V6:
+ case ARM11_DEBUG_V61: /* supports security extensions */
+ break;
+ default:
+ LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
return ERROR_FAIL;
}
- arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
- arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
+ arm11->brp = ((didr >> 24) & 0x0F) + 1;
+ arm11->wrp = ((didr >> 28) & 0x0F) + 1;
/** \todo TODO: reserve one brp slot if we allow breakpoints during step */
arm11->free_brps = arm11->brp;
arm11->free_wrps = arm11->wrp;
- LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
- arm11->device_id,
- (int)(arm11->implementor),
- arm11->didr);
+ LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
+ device_id, implementor, didr);
/* as a side-effect this reads DSCR and thus
* clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
if (retval != ERROR_OK)
return retval;
+ /* Build register cache "late", after target_init(), since we
+ * want to know if this core supports Secure Monitor mode.
+ */
+ if (!target_was_examined(target)) {
+ arm11_dpm_init(arm11, didr);
+ retval = arm_dpm_setup(&arm11->dpm);
+ }
+
/* ETM on ARM11 still uses original scanchain 6 access mode */
if (arm11->arm.etm && !target_was_examined(target)) {
*register_get_last_cache_p(&target->reg_cache) =
/** Load a register that is marked !valid in the register cache */
static int arm11_get_reg(struct reg *reg)
{
- FNC_INFO;
-
struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target;
if (target->state != TARGET_HALTED)
/** Change a value in the register cache */
static int arm11_set_reg(struct reg *reg, uint8_t *buf)
{
- FNC_INFO;
-
struct target *target = ((struct arm11_reg_state *)reg->arch_info)->target;
struct arm11_common *arm11 = target_to_arm11(target);
// const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
return ERROR_OK;
}
+static const struct reg_arch_type arm11_reg_type = {
+ .get = arm11_get_reg,
+ .set = arm11_set_reg,
+};
+
static int arm11_build_reg_cache(struct target *target)
{
struct arm11_common *arm11 = target_to_arm11(target);
-
- NEW(struct reg_cache, cache, 1);
- NEW(struct reg, reg_list, ARM11_REGCACHE_COUNT);
- NEW(struct arm11_reg_state, arm11_reg_states, ARM11_REGCACHE_COUNT);
-
- if (arm11_regs_arch_type == -1)
- arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
-
- register_init_dummy(&arm11_gdb_dummy_fp_reg);
- register_init_dummy(&arm11_gdb_dummy_fps_reg);
+ struct reg_cache *cache;
+ struct reg *reg_list;
+ struct arm11_reg_state *arm11_reg_states;
+
+ cache = calloc(1, sizeof *cache);
+ reg_list = calloc(ARM11_REGCACHE_COUNT, sizeof *reg_list);
+ arm11_reg_states = calloc(ARM11_REGCACHE_COUNT,
+ sizeof *arm11_reg_states);
+ if (!cache || !reg_list || !arm11_reg_states) {
+ free(cache);
+ free(reg_list);
+ free(arm11_reg_states);
+ return ERROR_FAIL;
+ }
arm11->reg_list = reg_list;
- /* Build the process context cache */
- cache->name = "arm11 registers";
- cache->next = NULL;
+ /* build cache for some of the debug registers */
+ cache->name = "arm11 debug registers";
cache->reg_list = reg_list;
cache->num_regs = ARM11_REGCACHE_COUNT;
(*cache_p) = cache;
arm11->core_cache = cache;
-// armv7m->process_context = cache;
size_t i;
/* Not very elegant assertion */
- if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
- ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
+ if (ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11->reg_values) ||
+ ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11_reg_defs) ||
ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
{
- LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
+ LOG_ERROR("BUG: arm11->reg_values inconsistent (%d %u %u %d)",
+ ARM11_REGCACHE_COUNT,
+ (unsigned) ARRAY_SIZE(arm11->reg_values),
+ (unsigned) ARRAY_SIZE(arm11_reg_defs),
+ ARM11_RC_MAX);
+ /* FIXME minimally, use a build_bug_on(X) mechanism;
+ * runtime exit() here is bad!
+ */
exit(-1);
}
r->value = (uint8_t *)(arm11->reg_values + i);
r->dirty = 0;
r->valid = 0;
- r->arch_type = arm11_regs_arch_type;
+ r->type = &arm11_reg_type;
r->arch_info = rs;
rs->def_index = i;
return ERROR_OK;
}
-static COMMAND_HELPER(arm11_handle_bool, bool *var, char *name)
-{
- if (argc == 0)
- {
- LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
- return ERROR_OK;
- }
-
- if (argc != 1)
- return ERROR_COMMAND_SYNTAX_ERROR;
-
- switch (args[0][0])
- {
- case '0': /* 0 */
- case 'f': /* false */
- case 'F':
- case 'd': /* disable */
- case 'D':
- *var = false;
- break;
-
- case '1': /* 1 */
- case 't': /* true */
- case 'T':
- case 'e': /* enable */
- case 'E':
- *var = true;
- break;
- }
-
- LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
-
- return ERROR_OK;
-}
+/* FIXME all these BOOL_WRAPPER things should be modifying
+ * per-instance state, not shared state; ditto the vector
+ * catch register support. Scan chains with multiple cores
+ * should be able to say "work with this core like this,
+ * that core like that". Example, ARM11 MPCore ...
+ */
-#define BOOL_WRAPPER(name, print_name) \
-COMMAND_HANDLER(arm11_handle_bool_##name) \
-{ \
- return CALL_COMMAND_HANDLER(arm11_handle_bool, \
- &arm11_config_##name, print_name); \
-}
+#define ARM11_BOOL_WRAPPER(name, print_name) \
+ COMMAND_HANDLER(arm11_handle_bool_##name) \
+ { \
+ return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
+ &arm11_config_##name, print_name); \
+ }
-BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
-BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
-BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
-BOOL_WRAPPER(hardware_step, "hardware single step")
+ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
+ARM11_BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
+ARM11_BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
+ARM11_BOOL_WRAPPER(hardware_step, "hardware single step")
COMMAND_HANDLER(arm11_handle_vcr)
{
- switch (argc) {
+ switch (CMD_ARGC) {
case 0:
break;
case 1:
- COMMAND_PARSE_NUMBER(u32, args[0], arm11_vcr);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11_vcr);
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
static int arm11_register_commands(struct command_context *cmd_ctx)
{
- FNC_INFO;
-
struct command *top_cmd, *mw_cmd;
- top_cmd = register_command(cmd_ctx, NULL, "arm11",
+ armv4_5_register_commands(cmd_ctx);
+
+ top_cmd = COMMAND_REGISTER(cmd_ctx, NULL, "arm11",
NULL, COMMAND_ANY, NULL);
/* "hardware_step" is only here to check if the default
* simulate + breakpoint implementation is broken.
* TEMPORARY! NOT DOCUMENTED!
*/
- register_command(cmd_ctx, top_cmd, "hardware_step",
+ COMMAND_REGISTER(cmd_ctx, top_cmd, "hardware_step",
arm11_handle_bool_hardware_step, COMMAND_ANY,
"DEBUG ONLY - Hardware single stepping"
" (default: disabled)");
- mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
+ mw_cmd = COMMAND_REGISTER(cmd_ctx, top_cmd, "memwrite",
NULL, COMMAND_ANY, NULL);
- register_command(cmd_ctx, mw_cmd, "burst",
+ COMMAND_REGISTER(cmd_ctx, mw_cmd, "burst",
arm11_handle_bool_memwrite_burst, COMMAND_ANY,
"Enable/Disable non-standard but fast burst mode"
" (default: enabled)");
- register_command(cmd_ctx, mw_cmd, "error_fatal",
+ COMMAND_REGISTER(cmd_ctx, mw_cmd, "error_fatal",
arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY,
"Terminate program if transfer error was found"
" (default: enabled)");
- register_command(cmd_ctx, top_cmd, "step_irq_enable",
+ COMMAND_REGISTER(cmd_ctx, top_cmd, "step_irq_enable",
arm11_handle_bool_step_irq_enable, COMMAND_ANY,
"Enable interrupts while stepping"
" (default: disabled)");
- register_command(cmd_ctx, top_cmd, "vcr",
+ COMMAND_REGISTER(cmd_ctx, top_cmd, "vcr",
arm11_handle_vcr, COMMAND_ANY,
"Control (Interrupt) Vector Catch Register");
.deassert_reset = arm11_deassert_reset,
.soft_reset_halt = arm11_soft_reset_halt,
- .get_gdb_reg_list = arm11_get_gdb_reg_list,
+ .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.read_memory = arm11_read_memory,
.write_memory = arm11_write_memory,
.add_watchpoint = arm11_add_watchpoint,
.remove_watchpoint = arm11_remove_watchpoint,
- .run_algorithm = arm11_run_algorithm,
+ .run_algorithm = armv4_5_run_algorithm,
.register_commands = arm11_register_commands,
.target_create = arm11_target_create,
projects / fw / openocd / blobdiff