static uint8_t ao_usb_tx2_count;
#endif
+#if AO_USB_HAS_IN3
+static uint16_t ao_usb_in_tx3_offset;
+static uint8_t ao_usb_in_tx3_which;
+static uint8_t ao_usb_tx3_count;
+#endif
+
/*
* End point register indices
*/
#define AO_USB_OUT_EPR 2
#define AO_USB_IN_EPR 3
#define AO_USB_IN2_EPR 4
+#define AO_USB_IN3_EPR 5
/* Marks when we don't need to send an IN packet.
* This happens only when the last IN packet is not full,
static uint8_t ao_usb_in2_flushed;
#endif
+#if AO_USB_HAS_IN3
+/* Marks when we have delivered an IN packet to the hardware
+ * and it has not been received yet. ao_sleep on this address
+ * to wait for it to be delivered.
+ */
+static uint8_t ao_usb_in3_pending;
+static uint16_t in3_count;
+static uint8_t ao_usb_in3_flushed;
+#endif
+
/* Marks when an OUT packet has been received by the hardware
* but not pulled to the shadow buffer.
*/
* Set current device address and mark the
* interface as active
*/
-void
+static void
ao_usb_set_address(uint8_t address)
{
debug("ao_usb_set_address %02x\n", address);
epr_old = epr_write = stm_usb.epr[ep].r;
epr_write &= STM_USB_EPR_PRESERVE_MASK;
epr_write |= STM_USB_EPR_INVARIANT;
- epr_write |= set_toggle(epr_old,
- STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX,
- stat_tx << STM_USB_EPR_STAT_TX);
+ epr_write |= (uint16_t) set_toggle(epr_old,
+ STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX,
+ stat_tx << STM_USB_EPR_STAT_TX);
stm_usb.epr[ep].r = epr_write;
_tx_dbg1("set_stat_tx bottom", epr_write);
}
epr_write = stm_usb.epr[ep].r;
epr_write &= STM_USB_EPR_PRESERVE_MASK;
epr_write |= STM_USB_EPR_INVARIANT;
- epr_write |= ((dtog_rx << STM_USB_EPR_DTOG_RX) |
- (dtog_tx << STM_USB_EPR_DTOG_TX));
+ epr_write |= (uint16_t) ((dtog_rx << STM_USB_EPR_DTOG_RX) |
+ (dtog_tx << STM_USB_EPR_DTOG_TX));
stm_usb.epr[ep].r = epr_write;
_tx_dbg1("toggle_dtog bottom", epr_write);
}
epr_write = epr_old = stm_usb.epr[ep].r;
epr_write &= STM_USB_EPR_PRESERVE_MASK;
epr_write |= STM_USB_EPR_INVARIANT;
- epr_write |= set_toggle(epr_old,
- STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX,
- stat_rx << STM_USB_EPR_STAT_RX);
+ epr_write |= (uint16_t) set_toggle(epr_old,
+ STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX,
+ stat_rx << STM_USB_EPR_STAT_RX);
stm_usb.epr[ep].r = epr_write;
}
ao_arch_block_interrupts();
epr = stm_usb.epr[ep].r;
- epr = ((0 << STM_USB_EPR_CTR_RX) |
- (type << STM_USB_EPR_EP_TYPE) |
- (kind << STM_USB_EPR_EP_KIND) |
- (0 << STM_USB_EPR_CTR_TX) |
- (addr << STM_USB_EPR_EA) |
- set_toggle(epr,
-
- (1 << STM_USB_EPR_DTOG_RX) |
- (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX) |
- (1 << STM_USB_EPR_DTOG_TX) |
- (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX),
-
- (dtog_rx << STM_USB_EPR_DTOG_RX) |
- (stat_rx << STM_USB_EPR_STAT_RX) |
- (dtog_tx << STM_USB_EPR_DTOG_TX) |
- (stat_tx << STM_USB_EPR_STAT_TX)));
+ epr = (uint16_t) ((0UL << STM_USB_EPR_CTR_RX) |
+ ((uint32_t) type << STM_USB_EPR_EP_TYPE) |
+ ((uint32_t) kind << STM_USB_EPR_EP_KIND) |
+ (0UL << STM_USB_EPR_CTR_TX) |
+ ((uint32_t) addr << STM_USB_EPR_EA) |
+ set_toggle(epr,
+
+ (1UL << STM_USB_EPR_DTOG_RX) |
+ (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX) |
+ (1UL << STM_USB_EPR_DTOG_TX) |
+ (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX),
+
+ ((uint32_t) dtog_rx << STM_USB_EPR_DTOG_RX) |
+ ((uint32_t) stat_rx << STM_USB_EPR_STAT_RX) |
+ ((uint32_t) dtog_tx << STM_USB_EPR_DTOG_TX) |
+ ((uint32_t) stat_tx << STM_USB_EPR_STAT_TX)));
stm_usb.epr[ep].r = epr;
ao_arch_release_interrupts();
debug ("writing epr[%d] 0x%04x wrote 0x%04x\n",
sram_addr += AO_USB_CONTROL_SIZE;
#if AO_USB_HAS_INT
- sram_addr += (sram_addr & 1);
+ sram_addr = (uint16_t) ((uint16_t) sram_addr + (uint16_t) (sram_addr & 1));
ao_usb_int_tx_offset = sram_addr;
sram_addr += AO_USB_INT_SIZE;
#endif
#if AO_USB_HAS_OUT
- sram_addr += (sram_addr & 1);
+ sram_addr = (uint16_t) ((uint16_t) sram_addr + (uint16_t) (sram_addr & 1));
ao_usb_out_rx_offset = sram_addr;
sram_addr += AO_USB_OUT_SIZE * 2;
#endif
#if AO_USB_HAS_IN
- sram_addr += (sram_addr & 1);
+ sram_addr = (uint16_t) ((uint16_t) sram_addr + (uint16_t) (sram_addr & 1));
ao_usb_in_tx_offset = sram_addr;
sram_addr += AO_USB_IN_SIZE * 2;
#endif
#if AO_USB_HAS_IN2
- sram_addr += (sram_addr & 1);
+ sram_addr = (uint16_t) ((uint16_t) sram_addr + (uint16_t) (sram_addr & 1));
ao_usb_in_tx2_offset = sram_addr;
sram_addr += AO_USB_IN_SIZE * 2;
#endif
+#if AO_USB_HAS_IN3
+ sram_addr = (uint16_t) ((uint16_t) sram_addr + (uint16_t) (sram_addr & 1));
+ ao_usb_in_tx3_offset = sram_addr;
+ sram_addr += AO_USB_IN_SIZE * 2;
+#endif
}
static void
static void
ao_usb_set_ep0(void)
{
- int e;
+ uint8_t e;
ao_usb_init_btable();
ao_usb_in_tx2_which = 0;
#endif
+#if AO_USB_HAS_IN3
+ /* Set up the IN3 end point */
+ stm_usb_bdt[AO_USB_IN3_EPR].double_tx[0].addr = ao_usb_in_tx3_offset;
+ stm_usb_bdt[AO_USB_IN3_EPR].double_tx[0].count = 0;
+ stm_usb_bdt[AO_USB_IN3_EPR].double_tx[1].addr = ao_usb_in_tx3_offset + AO_USB_IN_SIZE;
+ stm_usb_bdt[AO_USB_IN3_EPR].double_tx[1].count = 0;
+
+ ao_usb_init_ep(AO_USB_IN3_EPR,
+ AO_USB_IN3_EP,
+ STM_USB_EPR_EP_TYPE_BULK,
+ STM_USB_EPR_STAT_RX_DISABLED,
+ STM_USB_EPR_STAT_TX_NAK,
+ STM_USB_EPR_EP_KIND_DBL_BUF,
+ 0, 1);
+
+ /* First transmit data goes to buffer 0 */
+ ao_usb_in_tx3_which = 0;
+#endif
+
ao_usb_in_flushed = 0;
ao_usb_in_pending = 0;
ao_wakeup(&ao_usb_in_pending);
ao_wakeup(&ao_usb_in2_pending);
#endif
+#if AO_USB_HAS_IN3
+ ao_usb_in3_flushed = 0;
+ ao_usb_in3_pending = 0;
+ ao_wakeup(&ao_usb_in3_pending);
+#endif
+
ao_usb_out_avail = 0;
ao_usb_configuration = 0;
{
if (offset & 1)
ao_usb_packet_put(offset - 1,
- ao_usb_packet_get(offset - 1) | ((uint16_t) byte) << 8);
+ (uint16_t) (ao_usb_packet_get(offset - 1) | ((uint16_t) byte) << 8));
else
ao_usb_packet_put(offset, (uint16_t) byte);
}
if (len > ao_usb_ep0_out_len)
len = ao_usb_ep0_out_len;
- ao_usb_ep0_out_len -= len;
+ ao_usb_ep0_out_len -= (uint8_t) len;
/* Pull all of the data out of the packet */
debug_data ("Fill EP0 len %d:", len);
{
/* Don't send more than asked for */
if (ao_usb_ep0_in_len > max)
- ao_usb_ep0_in_len = max;
+ ao_usb_ep0_in_len = (uint8_t) max;
ao_usb_ep0_flush();
}
for (i = 28; i >= 0; i -= 4) {
uint8_t bits = (in >> i) & 0xf;
- *out++ = ((bits < 10) ? '0' : ('a' - 10)) + bits;
+ *out++ = (uint8_t) (((bits < 10) ? '0' : ('a' - 10)) + bits);
*out++ = 0;
}
}
ao_usb_get_descriptor(uint16_t value, uint16_t length)
{
const uint8_t *descriptor;
- uint8_t type = value >> 8;
- uint8_t index = value;
+ uint8_t type = (uint8_t) (value >> 8);
+ uint8_t index = (uint8_t) value;
descriptor = ao_usb_descriptors;
while (descriptor[0] != 0) {
}
#endif
if (len > length)
- len = length;
+ len = (uint8_t) length;
ao_usb_ep0_in_set(descriptor, len);
break;
}
break;
case AO_USB_REQ_SET_ADDRESS:
debug ("set address %d\n", ao_usb_setup.value);
- ao_usb_address = ao_usb_setup.value;
+ ao_usb_address = (uint8_t) ao_usb_setup.value;
ao_usb_address_pending = 1;
break;
case AO_USB_REQ_GET_DESCRIPTOR:
ao_usb_ep0_in_queue_byte(ao_usb_configuration);
break;
case AO_USB_REQ_SET_CONFIGURATION:
- ao_usb_configuration = ao_usb_setup.value;
+ ao_usb_configuration = (uint8_t) ao_usb_setup.value;
debug ("set configuration %d\n", ao_usb_configuration);
ao_usb_set_configuration();
break;
}
#if AO_POWER_MANAGEMENT
-void
+static void
ao_usb_suspend(void)
{
stm_usb.cntr |= (1 << STM_USB_CNTR_FSUSP);
ao_clock_suspend();
}
-void
+static void
ao_usb_wakeup(void)
{
ao_clock_resume();
- stm_usb.cntr &= ~(1 << STM_USB_CNTR_FSUSP);
+ stm_usb.cntr &= (uint16_t) ~(1 << STM_USB_CNTR_FSUSP);
ao_power_resume();
}
#endif
{
uint32_t istr = stm_usb.istr;
- stm_usb.istr = ~istr;
+ stm_usb.istr = (uint16_t) ~istr;
if (istr & (1 << STM_USB_ISTR_CTR)) {
uint8_t ep = istr & STM_USB_ISTR_EP_ID_MASK;
uint16_t epr, epr_write;
epr_write = epr;
epr_write &= STM_USB_EPR_PRESERVE_MASK;
epr_write |= STM_USB_EPR_INVARIANT;
- epr_write &= ~(1 << STM_USB_EPR_CTR_RX);
- epr_write &= ~(1 << STM_USB_EPR_CTR_TX);
+ epr_write &= (uint16_t) ~(1 << STM_USB_EPR_CTR_RX);
+ epr_write &= (uint16_t) ~(1 << STM_USB_EPR_CTR_TX);
stm_usb.epr[ep].r = epr_write;
switch (ep) {
ao_wakeup(&ao_usb_in2_pending);
}
break;
+#endif
+#if AO_USB_HAS_IN3
+ case AO_USB_IN3_EPR:
+ ++in3_count;
+ _tx_dbg1("TX3 ISR", epr);
+ if (ao_usb_epr_ctr_tx(epr)) {
+ ao_usb_in3_pending = 0;
+ ao_wakeup(&ao_usb_in3_pending);
+ }
+ break;
#endif
case AO_USB_INT_EPR:
#if USB_STATUS
_ao_usb_in_wait();
ao_usb_in_flushed = 0;
- ao_usb_tx_byte(ao_usb_in_tx_offset + AO_USB_IN_SIZE * ao_usb_in_tx_which + ao_usb_tx_count++, c);
+ ao_usb_tx_byte((uint16_t) (ao_usb_in_tx_offset + AO_USB_IN_SIZE * ao_usb_in_tx_which + ao_usb_tx_count++), c);
/* Send the packet when full */
if (ao_usb_tx_count == AO_USB_IN_SIZE) {
/* Toggle our usage */
ao_usb_in_tx2_which = 1 - ao_usb_in_tx2_which;
+ /* Toggle the SW_BUF flag */
+ _ao_usb_toggle_dtog(AO_USB_IN2_EPR, 1, 0);
+
/* Mark the outgoing buffer as valid */
_ao_usb_set_stat_tx(AO_USB_IN2_EPR, STM_USB_EPR_STAT_TX_VALID);
_ao_usb_in2_wait();
ao_usb_in2_flushed = 0;
- ao_usb_tx_byte(ao_usb_in_tx2_offset + AO_USB_IN_SIZE * ao_usb_in_tx2_which + ao_usb_tx2_count++, c);
+ ao_usb_tx_byte((uint16_t) (ao_usb_in_tx2_offset + AO_USB_IN_SIZE * ao_usb_in_tx2_which + ao_usb_tx2_count++), c);
/* Send the packet when full */
if (ao_usb_tx2_count == AO_USB_IN_SIZE) {
}
#endif
+#if AO_USB_HAS_IN3
+/* Queue the current IN buffer for transmission */
+static void
+_ao_usb_in3_send(void)
+{
+ _tx_dbg0("in3_send start");
+ debug ("send3 %d\n", ao_usb_tx3_count);
+ while (ao_usb_in3_pending)
+ ao_sleep(&ao_usb_in3_pending);
+ ao_usb_in3_pending = 1;
+ if (ao_usb_tx3_count != AO_USB_IN_SIZE)
+ ao_usb_in3_flushed = 1;
+ stm_usb_bdt[AO_USB_IN3_EPR].double_tx[ao_usb_in_tx3_which].count = ao_usb_tx3_count;
+ ao_usb_tx3_count = 0;
+
+ /* Toggle our usage */
+ ao_usb_in_tx3_which = 1 - ao_usb_in_tx3_which;
+
+ /* Toggle the SW_BUF flag */
+ _ao_usb_toggle_dtog(AO_USB_IN3_EPR, 1, 0);
+
+ /* Mark the outgoing buffer as valid */
+ _ao_usb_set_stat_tx(AO_USB_IN3_EPR, STM_USB_EPR_STAT_TX_VALID);
+
+ _tx_dbg0("in3_send end");
+}
+
+/* Wait for a free IN buffer. Interrupts are blocked */
+static void
+_ao_usb_in3_wait(void)
+{
+ for (;;) {
+ /* Check if the current buffer is writable */
+ if (ao_usb_tx3_count < AO_USB_IN_SIZE)
+ break;
+
+ _tx_dbg0("in3_wait top");
+ /* Wait for an IN buffer to be ready */
+ while (ao_usb_in3_pending)
+ ao_sleep(&ao_usb_in3_pending);
+ _tx_dbg0("in_wait bottom");
+ }
+}
+
+void
+ao_usb_flush3(void)
+{
+ if (!ao_usb_running)
+ return;
+
+ /* Anytime we've sent a character since
+ * the last time we flushed, we'll need
+ * to send a packet -- the only other time
+ * we would send a packet is when that
+ * packet was full, in which case we now
+ * want to send an empty packet
+ */
+ ao_arch_block_interrupts();
+ while (!ao_usb_in3_flushed) {
+ _tx_dbg0("flush3 top");
+ _ao_usb_in3_send();
+ _tx_dbg0("flush3 end");
+ }
+ ao_arch_release_interrupts();
+}
+
+void
+ao_usb_putchar3(char c)
+{
+ if (!ao_usb_running)
+ return;
+
+ ao_arch_block_interrupts();
+ _ao_usb_in3_wait();
+
+ ao_usb_in3_flushed = 0;
+ ao_usb_tx_byte((uint16_t) (ao_usb_in_tx3_offset + AO_USB_IN_SIZE * ao_usb_in_tx3_which + ao_usb_tx3_count++), c);
+
+ /* Send the packet when full */
+ if (ao_usb_tx3_count == AO_USB_IN_SIZE) {
+ _tx_dbg0("putchar3 full");
+ _ao_usb_in3_send();
+ _tx_dbg0("putchar3 flushed");
+ }
+ ao_arch_release_interrupts();
+}
+#endif
+
#if AO_USB_HAS_OUT
static void
_ao_usb_out_recv(void)
/* Switch to new buffer */
ao_usb_out_rx_which = 1 - ao_usb_out_rx_which;
- ao_usb_rx_count = stm_usb_bdt[AO_USB_OUT_EPR].double_rx[ao_usb_out_rx_which].count & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
+ ao_usb_rx_count = (uint8_t) (stm_usb_bdt[AO_USB_OUT_EPR].double_rx[ao_usb_out_rx_which].count & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK);
ao_usb_rx_pos = 0;
/* Toggle the SW_BUF_RX bit */
_rx_dbg1("out_recv count", ao_usb_rx_count);
}
-int
+static int
_ao_usb_pollchar(void)
{
uint8_t c;
}
/* Pull a character out of the fifo */
- c = ao_usb_rx_byte(ao_usb_out_rx_offset + ao_usb_out_rx_which * AO_USB_OUT_SIZE + ao_usb_rx_pos++);
+ c = ao_usb_rx_byte((uint16_t) (ao_usb_out_rx_offset + ao_usb_out_rx_which * AO_USB_OUT_SIZE + ao_usb_rx_pos++));
_rx_dbg1("char", c);
return c;
}
while ((c = _ao_usb_pollchar()) == AO_READ_AGAIN)
ao_sleep(AO_USB_OUT_SLEEP_ADDR);
ao_arch_release_interrupts();
- return c;
+ return (char) c;
}
#endif
stm_usb.istr = 0;
/* Disable USB pull-up */
- stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
+ stm_usb.bcdr &= (uint16_t) ~(1 << STM_USB_BCDR_DPPU);
/* Switch off the device */
stm_usb.cntr = (1 << STM_USB_CNTR_PDWN) | (1 << STM_USB_CNTR_FRES);
/* Disable the interface */
- stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_USBEN);
+ stm_rcc.apb1enr &= ~(1UL << STM_RCC_APB1ENR_USBEN);
ao_arch_release_interrupts();
}
int t;
/* Select HSI48 as USB clock source */
- stm_rcc.cfgr3 &= ~(1 << STM_RCC_CFGR3_USBSW);
+ stm_rcc.cfgr3 &= ~(1UL << STM_RCC_CFGR3_USBSW);
/* Enable USB device */
stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USBEN);
/* Clear reset condition */
- stm_rcc.apb1rstr &= ~(1 << STM_RCC_APB1RSTR_USBRST);
+ stm_rcc.apb1rstr &= ~(1UL << STM_RCC_APB1RSTR_USBRST);
/* Disable USB pull-up */
- stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
+ stm_usb.bcdr &= (uint16_t) ~(1 << STM_USB_BCDR_DPPU);
/* Do not touch the GPIOA configuration; USB takes priority
* over GPIO on pins A11 and A12, but if you select alternate
control_count, out_count, in_count, int_count, reset_count);
}
-__code struct ao_cmds ao_usb_cmds[] = {
+const struct ao_cmds ao_usb_cmds[] = {
{ ao_usb_irq, "I\0Show USB interrupt counts" },
{ 0, NULL }
};
#endif
};
-#define NUM_USB_DBG 128
+#define NUM_USB_DBG 16
-struct ao_usb_dbg dbg[128];
+struct ao_usb_dbg dbg[NUM_USB_DBG];
int dbg_i;
static void _dbg(int line, char *msg, uint32_t value)
asm("mrs %0,primask" : "=&r" (primask));
dbg[dbg_i].primask = primask;
#if TX_DBG
- dbg[dbg_i].in_count = in_count;
- dbg[dbg_i].in_epr = stm_usb.epr[AO_USB_IN_EPR];
- dbg[dbg_i].in_pending = ao_usb_in_pending;
- dbg[dbg_i].tx_count = ao_usb_tx_count;
- dbg[dbg_i].in_flushed = ao_usb_in_flushed;
+ dbg[dbg_i].in_count = in3_count;
+ dbg[dbg_i].in_epr = stm_usb.epr[AO_USB_IN3_EPR].r;
+ dbg[dbg_i].in_pending = ao_usb_in3_pending;
+ dbg[dbg_i].tx_count = ao_usb_tx3_count;
+ dbg[dbg_i].in_flushed = ao_usb_in3_flushed;
#endif
#if RX_DBG
dbg[dbg_i].rx_count = ao_usb_rx_count;