#include <stdint.h>
typedef volatile uint32_t vuint32_t;
+typedef volatile uint16_t vuint16_t;
typedef volatile void * vvoid_t;
struct stm_gpio {
};
#define STM_MODER_SHIFT(pin) ((pin) << 1)
-#define STM_MODER_MASK 3
+#define STM_MODER_MASK 3UL
#define STM_MODER_INPUT 0
#define STM_MODER_OUTPUT 1
#define STM_MODER_ALTERNATE 2
static inline void
stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
- gpio->moder = ((gpio->moder &
- ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
- value << STM_MODER_SHIFT(pin));
+ gpio->moder = (((uint32_t) gpio->moder &
+ (uint32_t) ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
+ (value << STM_MODER_SHIFT(pin)));
}
static inline uint32_t
}
#define STM_OTYPER_SHIFT(pin) (pin)
-#define STM_OTYPER_MASK 1
+#define STM_OTYPER_MASK 1UL
#define STM_OTYPER_PUSH_PULL 0
#define STM_OTYPER_OPEN_DRAIN 1
static inline void
stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
gpio->otyper = ((gpio->otyper &
- ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
- value << STM_OTYPER_SHIFT(pin));
+ (uint32_t) ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
+ (value << STM_OTYPER_SHIFT(pin)));
}
static inline uint32_t
}
#define STM_OSPEEDR_SHIFT(pin) ((pin) << 1)
-#define STM_OSPEEDR_MASK 3
+#define STM_OSPEEDR_MASK 3UL
#define STM_OSPEEDR_LOW 0
#define STM_OSPEEDR_MEDIUM 1
#define STM_OSPEEDR_HIGH 2
static inline void
stm_ospeedr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
gpio->ospeedr = ((gpio->ospeedr &
- ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
- value << STM_OSPEEDR_SHIFT(pin));
+ (uint32_t) ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
+ (value << STM_OSPEEDR_SHIFT(pin)));
}
static inline void
}
#define STM_PUPDR_SHIFT(pin) ((pin) << 1)
-#define STM_PUPDR_MASK 3
+#define STM_PUPDR_MASK 3UL
#define STM_PUPDR_NONE 0
#define STM_PUPDR_PULL_UP 1
#define STM_PUPDR_PULL_DOWN 2
static inline void
stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
gpio->pupdr = ((gpio->pupdr &
- ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
- value << STM_PUPDR_SHIFT(pin));
+ (uint32_t) ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
+ (value << STM_PUPDR_SHIFT(pin)));
}
static inline void
}
#define STM_AFR_SHIFT(pin) ((pin) << 2)
-#define STM_AFR_MASK 0xf
-#define STM_AFR_NONE 0
+#define STM_AFR_MASK 0xfUL
#define STM_AFR_AF0 0x0
#define STM_AFR_AF1 0x1
#define STM_AFR_AF2 0x2
stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
if (pin < 8)
gpio->afrl = ((gpio->afrl &
- ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
- value << STM_AFR_SHIFT(pin));
+ (uint32_t) ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
+ (value << STM_AFR_SHIFT(pin)));
else {
pin -= 8;
gpio->afrh = ((gpio->afrh &
- ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
- value << STM_AFR_SHIFT(pin));
+ (uint32_t) ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
+ (value << STM_AFR_SHIFT(pin)));
}
}
static inline uint16_t
stm_gpio_get_all(struct stm_gpio *gpio) {
- return gpio->idr;
+ return (uint16_t) gpio->idr;
}
/*
#define stm_usart1 (*((struct stm_usart *) 0x40013800))
#define stm_usart2 (*((struct stm_usart *) 0x40004400))
+struct stm_lpuart {
+ vuint32_t cr1;
+ vuint32_t cr2;
+ vuint32_t cr3;
+ vuint32_t brr;
+
+ uint32_t unused_10;
+ uint32_t unused_14;
+ vuint32_t rqr;
+ vuint32_t isr;
+
+ vuint32_t icr;
+ vuint32_t rdr;
+ vuint32_t tdr;
+};
+extern struct stm_lpuart stm_lpuart1;
+
+#define stm_lpuart1 (*((struct stm_lpuart *) 0x40004800))
+
+#define STM_LPUART_CR1_M1 28
+#define STM_LPUART_CR1_DEAT 21
+#define STM_LPUART_CR1_DEDT 16
+#define STM_LPUART_CR1_CMIE 14
+#define STM_LPUART_CR1_MME 13
+#define STM_LPUART_CR1_M0 12
+#define STM_LPUART_CR1_WAKE 11
+#define STM_LPUART_CR1_PCE 10
+#define STM_LPUART_CR1_PS 9
+#define STM_LPUART_CR1_PEIE 8
+#define STM_LPUART_CR1_TXEIE 7
+#define STM_LPUART_CR1_TCIE 6
+#define STM_LPUART_CR1_RXNEIE 5
+#define STM_LPUART_CR1_IDLEIE 4
+#define STM_LPUART_CR1_TE 3
+#define STM_LPUART_CR1_RE 2
+#define STM_LPUART_CR1_UESM 1
+#define STM_LPUART_CR1_UE 0
+
+#define STM_LPUART_CR2_ADD 24
+#define STM_LPUART_CR2_MSBFIRST 19
+#define STM_LPUART_CR2_DATAINV 18
+#define STM_LPUART_CR2_TXINV 17
+#define STM_LPUART_CR2_RXINV 16
+#define STM_LPUART_CR2_SWAP 15
+#define STM_LPUART_CR2_STOP 12
+#define STM_LPUART_CR2_ADDM7 4
+
+#define STM_LPUART_CR3_UCESM 23
+#define STM_LPUART_CR3_WUFIE 22
+#define STM_LPUART_CR3_WUS 20
+#define STM_LPUART_CR3_DEP 15
+#define STM_LPUART_CR3_DEM 14
+#define STM_LPUART_CR3_DDRE 13
+#define STM_LPUART_CR3_OVRDIS 12
+#define STM_LPUART_CR3_CTSIE 10
+#define STM_LPUART_CR3_CTSE 9
+#define STM_LPUART_CR3_RTSE 8
+#define STM_LPUART_CR3_DMAT 7
+#define STM_LPUART_CR3_DMAR 6
+#define STM_LPUART_CR3_HDSEL 3
+#define STM_LPUART_CR3_EIE 0
+
+#define STM_LPUART_RQR_RXFRQ 3
+#define STM_LPUART_RQR_MMRQ 2
+#define STM_LPUART_RQR_SBKRQ 1
+
+#define STM_LPUART_ISR_REACK 22
+#define STM_LPUART_ISR_TEACK 21
+#define STM_LPUART_ISR_WUF 20
+#define STM_LPUART_ISR_RWU 19
+#define STM_LPUART_ISR_SBKF 18
+#define STM_LPUART_ISR_CMF 17
+#define STM_LPUART_ISR_BUSY 16
+#define STM_LPUART_ISR_CTS 10
+#define STM_LPUART_ISR_CTSIF 9
+#define STM_LPUART_ISR_TXE 7
+#define STM_LPUART_ISR_TC 6
+#define STM_LPUART_ISR_RXNE 5
+#define STM_LPUART_ISR_IDLE 4
+#define STM_LPUART_ISR_ORE 3
+#define STM_LPUART_ISR_NF 2
+#define STM_LPUART_ISR_FE 1
+#define STM_LPUART_ISR_PE 1
+
+#define STM_LPUART_ICR_WUCF 20
+#define STM_LPUART_ICR_CMCF 17
+#define STM_LPUART_ICR_CTSCF 9
+#define STM_LPUART_ICR_TCCF 6
+#define STM_LPUART_ICR_IDLECF 4
+#define STM_LPUART_ICR_ORECF 3
+#define STM_LPUART_ICR_NCF 2
+#define STM_LPUART_ICR_FECF 1
+#define STM_LPUART_ICR_PECF 0
+
struct stm_tim {
};
#define STM_TIM1011_CR1_CKD_1 0
#define STM_TIM1011_CR1_CKD_2 1
#define STM_TIM1011_CR1_CKD_4 2
-#define STM_TIM1011_CR1_CKD_MASK 3
+#define STM_TIM1011_CR1_CKD_MASK 3UL
#define STM_TIM1011_CR1_ARPE 7
#define STM_TIM1011_CR1_URS 2
#define STM_TIM1011_CR1_UDIS 1
#define STM_TIM1011_SMCR_ETPS_2 1
#define STM_TIM1011_SMCR_ETPS_4 2
#define STM_TIM1011_SMCR_ETPS_8 3
-#define STM_TIM1011_SMCR_ETPS_MASK 3
+#define STM_TIM1011_SMCR_ETPS_MASK 3UL
#define STM_TIM1011_SMCR_ETF 8
#define STM_TIM1011_SMCR_ETF_NONE 0
#define STM_TIM1011_SMCR_ETF_CK_INT_2 1
#define STM_TIM1011_SMCR_ETF_DTS_32_5 13
#define STM_TIM1011_SMCR_ETF_DTS_32_6 14
#define STM_TIM1011_SMCR_ETF_DTS_32_8 15
-#define STM_TIM1011_SMCR_ETF_MASK 15
+#define STM_TIM1011_SMCR_ETF_MASK 15UL
#define STM_TIM1011_DIER_CC1E 1
#define STM_TIM1011_DIER_UIE 0
#define STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE 5
#define STM_TIM1011_CCMR1_OC1M_PWM_MODE_1 6
#define STM_TIM1011_CCMR1_OC1M_PWM_MODE_2 7
-#define STM_TIM1011_CCMR1_OC1M_MASK 7
+#define STM_TIM1011_CCMR1_OC1M_MASK 7UL
#define STM_TIM1011_CCMR1_OC1PE 3
#define STM_TIM1011_CCMR1_OC1FE 2
#define STM_TIM1011_CCMR1_CC1S 0
#define STM_TIM1011_CCMR1_CC1S_INPUT_TI1 1
#define STM_TIM1011_CCMR1_CC1S_INPUT_TI2 2
#define STM_TIM1011_CCMR1_CC1S_INPUT_TRC 3
-#define STM_TIM1011_CCMR1_CC1S_MASK 3
+#define STM_TIM1011_CCMR1_CC1S_MASK 3UL
#define STM_TIM1011_CCMR1_IC1F_NONE 0
#define STM_TIM1011_CCMR1_IC1F_CK_INT_2 1
#define STM_TIM1011_CCMR1_IC1F_DTS_32_5 13
#define STM_TIM1011_CCMR1_IC1F_DTS_32_6 14
#define STM_TIM1011_CCMR1_IC1F_DTS_32_8 15
-#define STM_TIM1011_CCMR1_IC1F_MASK 15
+#define STM_TIM1011_CCMR1_IC1F_MASK 15UL
#define STM_TIM1011_CCMR1_IC1PSC 2
#define STM_TIM1011_CCMR1_IC1PSC_1 0
#define STM_TIM1011_CCMR1_IC1PSC_2 1
#define STM_TIM1011_CCMR1_IC1PSC_4 2
#define STM_TIM1011_CCMR1_IC1PSC_8 3
-#define STM_TIM1011_CCMR1_IC1PSC_MASK 3
+#define STM_TIM1011_CCMR1_IC1PSC_MASK 3UL
#define STM_TIM1011_CCMR1_CC1S 0
#define STM_TIM1011_CCER_CC1NP 3
#define STM_TIM1011_TI1_RMP_LSI 1
#define STM_TIM1011_TI1_RMP_LSE 2
#define STM_TIM1011_TI1_RMP_RTC 3
-#define STM_TIM1011_TI1_RMP_MASK 3
-
-/* Flash interface */
-
-struct stm_flash {
- vuint32_t acr;
- vuint32_t pecr;
- vuint32_t pdkeyr;
- vuint32_t pekeyr;
-
- vuint32_t prgkeyr;
- vuint32_t optkeyr;
- vuint32_t sr;
- vuint32_t obr;
-
- vuint32_t wrpr;
-};
-
-extern struct stm_flash stm_flash;
-
-#define STM_FLASH_ACR_RUN_PD (4)
-#define STM_FLASH_ACR_SLEEP_PD (3)
-#define STM_FLASH_ACR_ACC64 (2)
-#define STM_FLASH_ACR_PRFEN (1)
-#define STM_FLASH_ACR_LATENCY (0)
-
-#define STM_FLASH_PECR_OBL_LAUNCH 18
-#define STM_FLASH_PECR_ERRIE 17
-#define STM_FLASH_PECR_EOPIE 16
-#define STM_FLASH_PECR_FPRG 10
-#define STM_FLASH_PECR_ERASE 9
-#define STM_FLASH_PECR_FTDW 8
-#define STM_FLASH_PECR_DATA 4
-#define STM_FLASH_PECR_PROG 3
-#define STM_FLASH_PECR_OPTLOCK 2
-#define STM_FLASH_PECR_PRGLOCK 1
-#define STM_FLASH_PECR_PELOCK 0
-
-#define STM_FLASH_SR_OPTVERR 11
-#define STM_FLASH_SR_SIZERR 10
-#define STM_FLASH_SR_PGAERR 9
-#define STM_FLASH_SR_WRPERR 8
-#define STM_FLASH_SR_READY 3
-#define STM_FLASH_SR_ENDHV 2
-#define STM_FLASH_SR_EOP 1
-#define STM_FLASH_SR_BSY 0
-
-#define STM_FLASH_PEKEYR_PEKEY1 0x89ABCDEF
-#define STM_FLASH_PEKEYR_PEKEY2 0x02030405
-
-#define STM_FLASH_PRGKEYR_PRGKEY1 0x8C9DAEBF
-#define STM_FLASH_PRGKEYR_PRGKEY2 0x13141516
+#define STM_TIM1011_TI1_RMP_MASK 3UL
struct stm_rcc {
vuint32_t cr;
/* Nominal high speed internal oscillator frequency is 16MHz */
#define STM_HSI_FREQ 16000000
-#define STM_MSI_FREQ 2097000
+#define STM_MSI_FREQ_65536 65536
+#define STM_MSI_FREQ_131072 131072
+#define STM_MSI_FREQ_262144 262144
+#define STM_MSI_FREQ_524288 524288
+#define STM_MSI_FREQ_1048576 1048576
+#define STM_MSI_FREQ_2097152 2097152
+#define STM_MSI_FREQ_4194304 4194304
#define STM_RCC_CR_RTCPRE (29)
#define STM_RCC_CR_RTCPRE_HSE_DIV_2 0
#define STM_RCC_CR_RTCPRE_HSE_DIV_4 1
#define STM_RCC_CR_RTCPRE_HSE_DIV_8 2
#define STM_RCC_CR_RTCPRE_HSE_DIV_16 3
-#define STM_RCC_CR_RTCPRE_HSE_MASK 3
+#define STM_RCC_CR_RTCPRE_HSE_MASK 3UL
#define STM_RCC_CR_CSSON (28)
#define STM_RCC_CR_PLLRDY (25)
#define STM_RCC_CR_HSIRDY (1)
#define STM_RCC_CR_HSION (0)
+#define STM_RCC_ICSCR_HSI16CAL 0
+#define STM_RCC_ICSCR_HSI16TRIM 8
+#define STM_RCC_ICSCR_MSIRANGE 13
+#define STM_RCC_ICSCR_MSIRANGE_65536 0
+#define STM_RCC_ICSCR_MSIRANGE_131072
+#define STM_RCC_ICSCR_MSIRANGE_262144 2
+#define STM_RCC_ICSCR_MSIRANGE_524288 3
+#define STM_RCC_ICSCR_MSIRANGE_1048576 4
+#define STM_RCC_ICSCR_MSIRANGE_2097152 5
+#define STM_RCC_ICSCR_MSIRANGE_4194304 6
+#define STM_RCC_ICSCR_MSIRANGE_MASK 0x7UL
+#define STM_RCC_ICSCR_MSICAL 16
+#define STM_RCC_ICSCR_MSITRIM 24
+
#define STM_RCC_CFGR_MCOPRE (28)
#define STM_RCC_CFGR_MCOPRE_DIV_1 0
#define STM_RCC_CFGR_MCOPRE_DIV_2 1
#define STM_RCC_CFGR_MCOPRE_DIV_4 2
#define STM_RCC_CFGR_MCOPRE_DIV_8 3
#define STM_RCC_CFGR_MCOPRE_DIV_16 4
-#define STM_RCC_CFGR_MCOPRE_MASK 7
+#define STM_RCC_CFGR_MCOPRE_MASK 7UL
#define STM_RCC_CFGR_MCOSEL (24)
#define STM_RCC_CFGR_MCOSEL_DISABLE 0
#define STM_RCC_CFGR_MCOSEL_PLL 5
#define STM_RCC_CFGR_MCOSEL_LSI 6
#define STM_RCC_CFGR_MCOSEL_LSE 7
-#define STM_RCC_CFGR_MCOSEL_MASK 7
+#define STM_RCC_CFGR_MCOSEL_MASK 7UL
#define STM_RCC_CFGR_PLLDIV (22)
#define STM_RCC_CFGR_PLLDIV_2 1
#define STM_RCC_CFGR_PLLDIV_3 2
#define STM_RCC_CFGR_PLLDIV_4 3
-#define STM_RCC_CFGR_PLLDIV_MASK 3
+#define STM_RCC_CFGR_PLLDIV_MASK 3UL
#define STM_RCC_CFGR_PLLMUL (18)
#define STM_RCC_CFGR_PLLMUL_3 0
#define STM_RCC_CFGR_PLLMUL_24 6
#define STM_RCC_CFGR_PLLMUL_32 7
#define STM_RCC_CFGR_PLLMUL_48 8
-#define STM_RCC_CFGR_PLLMUL_MASK 0xf
+#define STM_RCC_CFGR_PLLMUL_MASK 0xfUL
#define STM_RCC_CFGR_PLLSRC (16)
#define STM_RCC_CFGR_PPRE2_DIV_4 5
#define STM_RCC_CFGR_PPRE2_DIV_8 6
#define STM_RCC_CFGR_PPRE2_DIV_16 7
-#define STM_RCC_CFGR_PPRE2_MASK 7
+#define STM_RCC_CFGR_PPRE2_MASK 7UL
#define STM_RCC_CFGR_PPRE1 (8)
#define STM_RCC_CFGR_PPRE1_DIV_1 0
#define STM_RCC_CFGR_PPRE1_DIV_4 5
#define STM_RCC_CFGR_PPRE1_DIV_8 6
#define STM_RCC_CFGR_PPRE1_DIV_16 7
-#define STM_RCC_CFGR_PPRE1_MASK 7
+#define STM_RCC_CFGR_PPRE1_MASK 7UL
#define STM_RCC_CFGR_HPRE (4)
#define STM_RCC_CFGR_HPRE_DIV_1 0
#define STM_RCC_CFGR_HPRE_DIV_128 0xd
#define STM_RCC_CFGR_HPRE_DIV_256 0xe
#define STM_RCC_CFGR_HPRE_DIV_512 0xf
-#define STM_RCC_CFGR_HPRE_MASK 0xf
+#define STM_RCC_CFGR_HPRE_MASK 0xfUL
#define STM_RCC_CFGR_SWS (2)
#define STM_RCC_CFGR_SWS_MSI 0
#define STM_RCC_CFGR_SWS_HSI 1
#define STM_RCC_CFGR_SWS_HSE 2
#define STM_RCC_CFGR_SWS_PLL 3
-#define STM_RCC_CFGR_SWS_MASK 3
+#define STM_RCC_CFGR_SWS_MASK 3UL
#define STM_RCC_CFGR_SW (0)
#define STM_RCC_CFGR_SW_MSI 0
#define STM_RCC_CFGR_SW_HSI 1
#define STM_RCC_CFGR_SW_HSE 2
#define STM_RCC_CFGR_SW_PLL 3
-#define STM_RCC_CFGR_SW_MASK 3
+#define STM_RCC_CFGR_SW_MASK 3UL
#define STM_RCC_IOPENR_IOPAEN 0
#define STM_RCC_IOPENR_IOPBEN 1
#define STM_RCC_APB2ENR_DBGEN (22)
#define STM_RCC_APB2ENR_USART1EN (14)
#define STM_RCC_APB2ENR_SPI1EN (12)
-#define STM_RCC_APB2ENR_ADC1EN (9)
+#define STM_RCC_APB2ENR_ADCEN (9)
#define STM_RCC_APB2ENR_FWEN (7)
#define STM_RCC_APB2ENR_TIM22EN (5)
#define STM_RCC_APB2ENR_TIM21EN (2)
#define STM_RCC_APB1ENR_TIM3EN 1
#define STM_RCC_APB1ENR_TIM2EN 0
+#define STM_RCC_CCIPR_LPTIM1SEL 18
+#define STM_RCC_CCIPR_I2C3SEL 16
+#define STM_RCC_CCIPR_I2C1SEL 12
+#define STM_RCC_CCIPR_LPUART1SEL 10
+#define STM_RCC_CCIPR_LPUART1SEL_APB 0
+#define STM_RCC_CCIPR_LPUART1SEL_SYSTEM 1
+#define STM_RCC_CCIPR_LPUART1SEL_HSI16 2
+#define STM_RCC_CCIPR_LPUART1SEL_LSE 3
+#define STM_RCC_CCIPR_USART2SEL 2
+#define STM_RCC_CCIPR_USART1SEL 0
+
#define STM_RCC_CSR_LPWRRSTF (31)
#define STM_RCC_CSR_WWDGRSTF (30)
#define STM_RCC_CSR_IWDGRSTF (29)
#define STM_RCC_CSR_RTCSEL_LSE 1
#define STM_RCC_CSR_RTCSEL_LSI 2
#define STM_RCC_CSR_RTCSEL_HSE 3
-#define STM_RCC_CSR_RTCSEL_MASK 3
+#define STM_RCC_CSR_RTCSEL_MASK 3UL
#define STM_RCC_CSR_LSEBYP (10)
#define STM_RCC_CSR_LSERDY (9)
extern struct stm_pwr stm_pwr;
-#define STM_PWR_CR_LPRUN (14)
-#define STM_PWR_CR_VOS (11)
+#define STM_PWR_CR_LPDS 16
+#define STM_PWR_CR_LPRUN 14
+#define STM_PWR_CR_DS_EE_KOFF 13
+#define STM_PWR_CR_VOS 11
#define STM_PWR_CR_VOS_1_8 1
#define STM_PWR_CR_VOS_1_5 2
#define STM_PWR_CR_VOS_1_2 3
-#define STM_PWR_CR_VOS_MASK 3
-
-#define STM_PWR_CR_FWU (10)
-#define STM_PWR_CR_ULP (9)
-#define STM_PWR_CR_DBP (8)
-
-#define STM_PWR_CR_PLS (5)
+#define STM_PWR_CR_VOS_MASK 3UL
+#define STM_PWR_CR_FWU 10
+#define STM_PWR_CR_ULP 9
+#define STM_PWR_CR_DBP 8
+#define STM_PWR_CR_PLS 5
#define STM_PWR_CR_PLS_1_9 0
#define STM_PWR_CR_PLS_2_1 1
#define STM_PWR_CR_PLS_2_3 2
#define STM_PWR_CR_PLS_2_9 5
#define STM_PWR_CR_PLS_3_1 6
#define STM_PWR_CR_PLS_EXT 7
-#define STM_PWR_CR_PLS_MASK 7
-
-#define STM_PWR_CR_PVDE (4)
-#define STM_PWR_CR_CSBF (3)
-#define STM_PWR_CR_CWUF (2)
-#define STM_PWR_CR_PDDS (1)
-#define STM_PWR_CR_LPSDSR (0)
+#define STM_PWR_CR_PLS_MASK 7UL
+#define STM_PWR_CR_PVDE 4
+#define STM_PWR_CR_CSBF 3
+#define STM_PWR_CR_CWUF 2
+#define STM_PWR_CR_PDDS 1
+#define STM_PWR_CR_LPSDSR 0
#define STM_PWR_CSR_EWUP3 (10)
#define STM_PWR_CSR_EWUP2 (9)
#define STM_TIM67_CR2_MMS_RESET 0
#define STM_TIM67_CR2_MMS_ENABLE 1
#define STM_TIM67_CR2_MMS_UPDATE 2
-#define STM_TIM67_CR2_MMS_MASK 7
+#define STM_TIM67_CR2_MMS_MASK 7UL
#define STM_TIM67_DIER_UDE (8)
#define STM_TIM67_DIER_UIE (0)
#define STM_LCD_CR_BIAS_1_4 0
#define STM_LCD_CR_BIAS_1_2 1
#define STM_LCD_CR_BIAS_1_3 2
-#define STM_LCD_CR_BIAS_MASK 3
+#define STM_LCD_CR_BIAS_MASK 3UL
#define STM_LCD_CR_DUTY (2)
#define STM_LCD_CR_DUTY_STATIC 0
#define STM_LCD_CR_DUTY_1_3 2
#define STM_LCD_CR_DUTY_1_4 3
#define STM_LCD_CR_DUTY_1_8 4
-#define STM_LCD_CR_DUTY_MASK 7
+#define STM_LCD_CR_DUTY_MASK 7UL
#define STM_LCD_CR_VSEL (1)
#define STM_LCD_CR_LCDEN (0)
#define STM_LCD_FCR_PS_8192 0xd
#define STM_LCD_FCR_PS_16384 0xe
#define STM_LCD_FCR_PS_32768 0xf
-#define STM_LCD_FCR_PS_MASK 0xf
+#define STM_LCD_FCR_PS_MASK 0xfUL
#define STM_LCD_FCR_DIV (18)
#define STM_LCD_FCR_DIV_16 0x0
#define STM_LCD_FCR_DIV_29 0xd
#define STM_LCD_FCR_DIV_30 0xe
#define STM_LCD_FCR_DIV_31 0xf
-#define STM_LCD_FCR_DIV_MASK 0xf
+#define STM_LCD_FCR_DIV_MASK 0xfUL
#define STM_LCD_FCR_BLINK (16)
#define STM_LCD_FCR_BLINK_DISABLE 0
#define STM_LCD_FCR_BLINK_SEG0_COM0 1
#define STM_LCD_FCR_BLINK_SEG0_COMALL 2
#define STM_LCD_FCR_BLINK_SEGALL_COMALL 3
-#define STM_LCD_FCR_BLINK_MASK 3
+#define STM_LCD_FCR_BLINK_MASK 3UL
#define STM_LCD_FCR_BLINKF (13)
#define STM_LCD_FCR_BLINKF_8 0
#define STM_LCD_FCR_BLINKF_256 5
#define STM_LCD_FCR_BLINKF_512 6
#define STM_LCD_FCR_BLINKF_1024 7
-#define STM_LCD_FCR_BLINKF_MASK 7
+#define STM_LCD_FCR_BLINKF_MASK 7UL
#define STM_LCD_FCR_CC (10)
-#define STM_LCD_FCR_CC_MASK 7
+#define STM_LCD_FCR_CC_MASK 7UL
#define STM_LCD_FCR_DEAD (7)
-#define STM_LCD_FCR_DEAD_MASK 7
+#define STM_LCD_FCR_DEAD_MASK 7UL
#define STM_LCD_FCR_PON (4)
-#define STM_LCD_FCR_PON_MASK 7
+#define STM_LCD_FCR_PON_MASK 7UL
#define STM_LCD_FCR_UDDIE (3)
#define STM_LCD_FCR_SOFIE (1)
uint32_t v;
v = stm_nvic.ipr[n];
- v &= ~IRQ_PRIO_MASK(irq);
+ v &= (uint32_t) ~IRQ_PRIO_MASK(irq);
v |= (prio) << IRQ_PRIO_BIT(irq);
stm_nvic.ipr[n] = v;
}
#define STM_SCB_AIRCR_VECTCLRACTIVE 1
#define STM_SCB_AIRCR_VECTRESET 0
+#define STM_SCB_SCR_SVONPEND 4
+#define STM_SCB_SCR_SLEEPDEEP 2
+#define STM_SCB_SCR_SLEEPONEXIT 1
+
struct stm_mpu {
vuint32_t typer;
vuint32_t cr;
extern struct stm_mpu stm_mpu;
#define STM_MPU_TYPER_IREGION 16
-#define STM_MPU_TYPER_IREGION_MASK 0xff
+#define STM_MPU_TYPER_IREGION_MASK 0xffUL
#define STM_MPU_TYPER_DREGION 8
-#define STM_MPU_TYPER_DREGION_MASK 0xff
+#define STM_MPU_TYPER_DREGION_MASK 0xffUL
#define STM_MPU_TYPER_SEPARATE 0
#define STM_MPU_CR_PRIVDEFENA 2
#define STM_MPU_CR_ENABLE 0
#define STM_MPU_RNR_REGION 0
-#define STM_MPU_RNR_REGION_MASK 0xff
+#define STM_MPU_RNR_REGION_MASK 0xffUL
#define STM_MPU_RBAR_ADDR 5
-#define STM_MPU_RBAR_ADDR_MASK 0x7ffffff
+#define STM_MPU_RBAR_ADDR_MASK 0x7ffffffUL
#define STM_MPU_RBAR_VALID 4
#define STM_MPU_RBAR_REGION 0
-#define STM_MPU_RBAR_REGION_MASK 0xf
+#define STM_MPU_RBAR_REGION_MASK 0xfUL
#define STM_MPU_RASR_XN 28
#define STM_MPU_RASR_AP 24
#define STM_MPU_RASR_AP_RW_RW 3
#define STM_MPU_RASR_AP_RO_NONE 5
#define STM_MPU_RASR_AP_RO_RO 6
-#define STM_MPU_RASR_AP_MASK 7
+#define STM_MPU_RASR_AP_MASK 7UL
#define STM_MPU_RASR_TEX 19
-#define STM_MPU_RASR_TEX_MASK 7
+#define STM_MPU_RASR_TEX_MASK 7UL
#define STM_MPU_RASR_S 18
#define STM_MPU_RASR_C 17
#define STM_MPU_RASR_B 16
#define STM_MPU_RASR_SRD 8
-#define STM_MPU_RASR_SRD_MASK 0xff
+#define STM_MPU_RASR_SRD_MASK 0xffUL
#define STM_MPU_RASR_SIZE 1
-#define STM_MPU_RASR_SIZE_MASK 0x1f
+#define STM_MPU_RASR_SIZE_MASK 0x1fUL
#define STM_MPU_RASR_ENABLE 0
#define isr_decl(name) void stm_ ## name ## _isr(void)
#define STM_SYSCFG_MEMRMP_MEM_MODE_MAIN_FLASH 0
#define STM_SYSCFG_MEMRMP_MEM_MODE_SYSTEM_FLASH 1
#define STM_SYSCFG_MEMRMP_MEM_MODE_SRAM 3
-#define STM_SYSCFG_MEMRMP_MEM_MODE_MASK 3
+#define STM_SYSCFG_MEMRMP_MEM_MODE_MASK 3UL
#define STM_SYSCFG_PMC_USB_PU 0
#define STM_SYSCFG_EXTICR_PH 5
static inline void
-stm_exticr_set(struct stm_gpio *gpio, int pin) {
+stm_exticr_set(struct stm_gpio *gpio, uint8_t pin) {
uint8_t reg = pin >> 2;
uint8_t shift = (pin & 3) << 2;
uint8_t val = 0;
else if (gpio == &stm_gpioe)
val = STM_SYSCFG_EXTICR_PE;
- stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
+ stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xfUL << shift)) | val << shift;
}
struct stm_dma_channel {
vuint32_t isr;
vuint32_t ifcr;
struct stm_dma_channel channel[STM_NUM_DMA];
+ uint8_t unused94[0xa8 - 0x94];
+ vuint32_t cselr;
};
-extern struct stm_dma stm_dma;
+extern struct stm_dma stm_dma1;
+#define stm_dma1 (*(struct stm_dma *) 0x40020000)
/* DMA channels go from 1 to 7, instead of 0 to 6 (sigh)
*/
#define STM_DMA_INDEX(channel) ((channel) - 1)
#define STM_DMA_ISR(index) ((index) << 2)
-#define STM_DMA_ISR_MASK 0xf
+#define STM_DMA_ISR_MASK 0xfUL
#define STM_DMA_ISR_TEIF 3
#define STM_DMA_ISR_HTIF 2
#define STM_DMA_ISR_TCIF 1
#define STM_DMA_ISR_GIF 0
#define STM_DMA_IFCR(index) ((index) << 2)
-#define STM_DMA_IFCR_MASK 0xf
+#define STM_DMA_IFCR_MASK 0xfUL
#define STM_DMA_IFCR_CTEIF 3
#define STM_DMA_IFCR_CHTIF 2
#define STM_DMA_IFCR_CTCIF 1
#define STM_DMA_CCR_TCIE (1)
#define STM_DMA_CCR_EN (0)
-#define STM_DMA_CHANNEL_ADC1 1
-#define STM_DMA_CHANNEL_SPI1_RX 2
-#define STM_DMA_CHANNEL_SPI1_TX 3
-#define STM_DMA_CHANNEL_SPI2_RX 4
-#define STM_DMA_CHANNEL_SPI2_TX 5
-#define STM_DMA_CHANNEL_USART3_TX 2
-#define STM_DMA_CHANNEL_USART3_RX 3
-#define STM_DMA_CHANNEL_USART1_TX 4
-#define STM_DMA_CHANNEL_USART1_RX 5
-#define STM_DMA_CHANNEL_USART2_RX 6
-#define STM_DMA_CHANNEL_USART2_TX 7
-#define STM_DMA_CHANNEL_I2C2_TX 4
-#define STM_DMA_CHANNEL_I2C2_RX 5
-#define STM_DMA_CHANNEL_I2C1_TX 6
-#define STM_DMA_CHANNEL_I2C1_RX 7
-#define STM_DMA_CHANNEL_TIM2_CH3 1
-#define STM_DMA_CHANNEL_TIM2_UP 2
-#define STM_DMA_CHANNEL_TIM2_CH1 5
-#define STM_DMA_CHANNEL_TIM2_CH2 7
-#define STM_DMA_CHANNEL_TIM2_CH4 7
-#define STM_DMA_CHANNEL_TIM3_CH3 2
-#define STM_DMA_CHANNEL_TIM3_CH4 3
-#define STM_DMA_CHANNEL_TIM3_UP 3
-#define STM_DMA_CHANNEL_TIM3_CH1 6
-#define STM_DMA_CHANNEL_TIM3_TRIG 6
-#define STM_DMA_CHANNEL_TIM4_CH1 1
-#define STM_DMA_CHANNEL_TIM4_CH2 4
-#define STM_DMA_CHANNEL_TIM4_CH3 5
-#define STM_DMA_CHANNEL_TIM4_UP 7
-#define STM_DMA_CHANNEL_TIM6_UP_DA 2
-#define STM_DMA_CHANNEL_C_CHANNEL1 2
-#define STM_DMA_CHANNEL_TIM7_UP_DA 3
-#define STM_DMA_CHANNEL_C_CHANNEL2 3
-
-/*
- * Only spi channel 1 and 2 can use DMA
- */
-#define STM_NUM_SPI 2
+#define STM_DMA_CSELR_C7S_SPI2_TX 0x2
+#define STM_DMA_CSELR_C7S_USART2_TX 0x4
+#define STM_DMA_CSELR_C7S_LPUART1_TX 0x5
+#define STM_DMA_CSELR_C7S_I2C1_RX 0x6
+#define STM_DMA_CSELR_C7S_TIM2_CH2_TIM2_CH4 0x8
+#define STM_DMA_CSELR_C7S_USART4_TX 0xc
+#define STM_DMA_CSELR_C7S_USART5_TX 0xd
+
+#define STM_DMA_CSELR_C6S_SPI2_RX 0x2
+#define STM_DMA_CSELR_C6S_USART2_RX 0x4
+#define STM_DMA_CSELR_C6S_LPUART1_RX 0x5
+#define STM_DMA_CSELR_C6S_I2C1_TX 0x6
+#define STM_DMA_CSELR_C6S_TIM3_TRIG 0xa
+#define STM_DMA_CSELR_C6S_USART4_RX 0xc
+#define STM_DMA_CSELR_C6S_USART5_RX 0xd
+
+#define STM_DMA_CSELR_C5S_SPI2_TX 0x2
+#define STM_DMA_CSELR_C5S_USART1_RX 0x3
+#define STM_DMA_CSELR_C5S_USART2_RX 0x4
+#define STM_DMA_CSELR_C5S_I2C2_RX 0x7
+#define STM_DMA_CSELR_C5S_TIM2_CH1 0x8
+#define STM_DMA_CSELR_C5S_TIM3_CH1 0xa
+#define STM_DMA_CSELR_C5S_AES_IN 0xb
+#define STM_DMA_CSELR_C5S_I2C3_RX 0xe
+
+#define STM_DMA_CSELR_C4S_SPI2_RX 0x2
+#define STM_DMA_CSELR_C4S_USART1_TX 0x3
+#define STM_DMA_CSELR_C4S_USART2_TX 0x4
+#define STM_DMA_CSELR_C4S_I2C2_TX 0x7
+#define STM_DMA_CSELR_C4S_TIM2_CH4 0x8
+#define STM_DMA_CSELR_C4S_I2C3_TX 0xe
+#define STM_DMA_CSELR_C4S_TIM7_UP 0xf
+
+#define STM_DMA_CSELR_C3S_SPI1_TX 0x1
+#define STM_DMA_CSELR_C3S_USART1_RX 0x3
+#define STM_DMA_CSELR_C3S_LPUART1_RX 0x5
+#define STM_DMA_CSELR_C3S_I2C1_RX 0x6
+#define STM_DMA_CSELR_C3S_TIM2_CH2 0x8
+#define STM_DMA_CSELR_C3S_TIM4_CH4_TIM4_UP 0xa
+#define STM_DMA_CSELR_C3S_AES_OUT 0xb
+#define STM_DMA_CSELR_C3S_USART4_TX 0xc
+#define STM_DMA_CSELR_C3S_USART5_TX 0xd
+#define STM_DMA_CSELR_C3S_I2C3_RX 0xe
+
+#define STM_DMA_CSELR_C2S_ADC 0x0
+#define STM_DMA_CSELR_C2S_SPI1_RX 0x1
+#define STM_DMA_CSELR_C2S_USART1_TX 0x3
+#define STM_DMA_CSELR_C2S_LPUART1_TX 0x5
+#define STM_DMA_CSELR_C2S_I2C1_TX 0x6
+#define STM_DMA_CSELR_C2S_TIM2_UP 0x8
+#define STM_DMA_CSELR_C2S_TIM6_UP 0x9
+#define STM_DMA_CSELR_C2S_TIM3_CH3 0xa
+#define STM_DMA_CSELR_C2S_AES_OUT 0xb
+#define STM_DMA_CSELR_C2S_USART4_RX 0xc
+#define STM_DMA_CSELR_C2S_USART5_RX 0xd
+#define STM_DMA_CSELR_C2S_I2C3_TX 0xe
+
+#define STM_DMA_CSELR_C1S_ADC 0x0
+#define STM_DMA_CSELR_C1S_TIM2_CH3 0x8
+#define STM_DMA_CSELR_C1S_AES_IN 0xb
+
+#define STM_NUM_SPI 1
struct stm_spi {
vuint32_t cr1;
vuint32_t txcrcr;
};
-extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
+extern struct stm_spi stm_spi1;
+#define stm_spi1 (*(struct stm_spi *) 0x40013000)
/* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
*/
#define STM_SPI_CR1_BR_PCLK_64 5
#define STM_SPI_CR1_BR_PCLK_128 6
#define STM_SPI_CR1_BR_PCLK_256 7
-#define STM_SPI_CR1_BR_MASK 7
+#define STM_SPI_CR1_BR_MASK 7UL
#define STM_SPI_CR1_MSTR 2
#define STM_SPI_CR1_CPOL 1
#define STM_SPI_SR_RXNE 0
struct stm_adc {
- vuint32_t sr;
- vuint32_t cr1;
- vuint32_t cr2;
- vuint32_t smpr1;
- vuint32_t smpr2;
- vuint32_t smpr3;
- vuint32_t jofr1;
- vuint32_t jofr2;
- vuint32_t jofr3;
- vuint32_t jofr4;
- vuint32_t htr;
- vuint32_t ltr;
- vuint32_t sqr1;
- vuint32_t sqr2;
- vuint32_t sqr3;
- vuint32_t sqr4;
- vuint32_t sqr5;
- vuint32_t jsqr;
- vuint32_t jdr1;
- vuint32_t jdr2;
- vuint32_t jdr3;
- vuint32_t jdr4;
+ vuint32_t isr;
+ vuint32_t ier;
+ vuint32_t cr;
+ vuint32_t cfgr1;
+
+ vuint32_t cfgr2;
+ vuint32_t smpr;
+ vuint32_t r_18;
+ vuint32_t r_1c;
+
+ vuint32_t tr;
+ vuint32_t r_24;
+ vuint32_t chselr;
+ vuint32_t r_2c;
+
+ vuint32_t r_30[4];
+
vuint32_t dr;
- uint8_t reserved[0x300 - 0x5c];
- vuint32_t csr;
+
+ uint8_t r_44[0xb4 - 0x44];
+
+ vuint32_t calfact;
+
+ uint8_t r_b8[0x308 - 0xb8];
vuint32_t ccr;
};
extern struct stm_adc stm_adc;
-
-#define STM_ADC_SQ_TEMP 16
-#define STM_ADC_SQ_V_REF 17
-
-#define STM_ADC_SR_JCNR 9
-#define STM_ADC_SR_RCNR 8
-#define STM_ADC_SR_ADONS 6
-#define STM_ADC_SR_OVR 5
-#define STM_ADC_SR_STRT 4
-#define STM_ADC_SR_JSTRT 3
-#define STM_ADC_SR_JEOC 2
-#define STM_ADC_SR_EOC 1
-#define STM_ADC_SR_AWD 0
-
-#define STM_ADC_CR1_OVRIE 26
-#define STM_ADC_CR1_RES 24
-#define STM_ADC_CR1_RES_12 0
-#define STM_ADC_CR1_RES_10 1
-#define STM_ADC_CR1_RES_8 2
-#define STM_ADC_CR1_RES_6 3
-#define STM_ADC_CR1_RES_MASK 3
-#define STM_ADC_CR1_AWDEN 23
-#define STM_ADC_CR1_JAWDEN 22
-#define STM_ADC_CR1_PDI 17
-#define STM_ADC_CR1_PDD 16
-#define STM_ADC_CR1_DISCNUM 13
-#define STM_ADC_CR1_DISCNUM_1 0
-#define STM_ADC_CR1_DISCNUM_2 1
-#define STM_ADC_CR1_DISCNUM_3 2
-#define STM_ADC_CR1_DISCNUM_4 3
-#define STM_ADC_CR1_DISCNUM_5 4
-#define STM_ADC_CR1_DISCNUM_6 5
-#define STM_ADC_CR1_DISCNUM_7 6
-#define STM_ADC_CR1_DISCNUM_8 7
-#define STM_ADC_CR1_DISCNUM_MASK 7
-#define STM_ADC_CR1_JDISCEN 12
-#define STM_ADC_CR1_DISCEN 11
-#define STM_ADC_CR1_JAUTO 10
-#define STM_ADC_CR1_AWDSGL 9
-#define STM_ADC_CR1_SCAN 8
-#define STM_ADC_CR1_JEOCIE 7
-#define STM_ADC_CR1_AWDIE 6
-#define STM_ADC_CR1_EOCIE 5
-#define STM_ADC_CR1_AWDCH 0
-#define STM_ADC_CR1_AWDCH_MASK 0x1f
-
-#define STM_ADC_CR2_SWSTART 30
-#define STM_ADC_CR2_EXTEN 28
-#define STM_ADC_CR2_EXTEN_DISABLE 0
-#define STM_ADC_CR2_EXTEN_RISING 1
-#define STM_ADC_CR2_EXTEN_FALLING 2
-#define STM_ADC_CR2_EXTEN_BOTH 3
-#define STM_ADC_CR2_EXTEN_MASK 3
-#define STM_ADC_CR2_EXTSEL 24
-#define STM_ADC_CR2_EXTSEL_TIM9_CC2 0
-#define STM_ADC_CR2_EXTSEL_TIM9_TRGO 1
-#define STM_ADC_CR2_EXTSEL_TIM2_CC3 2
-#define STM_ADC_CR2_EXTSEL_TIM2_CC2 3
-#define STM_ADC_CR2_EXTSEL_TIM3_TRGO 4
-#define STM_ADC_CR2_EXTSEL_TIM4_CC4 5
-#define STM_ADC_CR2_EXTSEL_TIM2_TRGO 6
-#define STM_ADC_CR2_EXTSEL_TIM3_CC1 7
-#define STM_ADC_CR2_EXTSEL_TIM3_CC3 8
-#define STM_ADC_CR2_EXTSEL_TIM4_TRGO 9
-#define STM_ADC_CR2_EXTSEL_TIM6_TRGO 10
-#define STM_ADC_CR2_EXTSEL_EXTI_11 15
-#define STM_ADC_CR2_EXTSEL_MASK 15
-#define STM_ADC_CR2_JWSTART 22
-#define STM_ADC_CR2_JEXTEN 20
-#define STM_ADC_CR2_JEXTEN_DISABLE 0
-#define STM_ADC_CR2_JEXTEN_RISING 1
-#define STM_ADC_CR2_JEXTEN_FALLING 2
-#define STM_ADC_CR2_JEXTEN_BOTH 3
-#define STM_ADC_CR2_JEXTEN_MASK 3
-#define STM_ADC_CR2_JEXTSEL 16
-#define STM_ADC_CR2_JEXTSEL_TIM9_CC1 0
-#define STM_ADC_CR2_JEXTSEL_TIM9_TRGO 1
-#define STM_ADC_CR2_JEXTSEL_TIM2_TRGO 2
-#define STM_ADC_CR2_JEXTSEL_TIM2_CC1 3
-#define STM_ADC_CR2_JEXTSEL_TIM3_CC4 4
-#define STM_ADC_CR2_JEXTSEL_TIM4_TRGO 5
-#define STM_ADC_CR2_JEXTSEL_TIM4_CC1 6
-#define STM_ADC_CR2_JEXTSEL_TIM4_CC2 7
-#define STM_ADC_CR2_JEXTSEL_TIM4_CC3 8
-#define STM_ADC_CR2_JEXTSEL_TIM10_CC1 9
-#define STM_ADC_CR2_JEXTSEL_TIM7_TRGO 10
-#define STM_ADC_CR2_JEXTSEL_EXTI_15 15
-#define STM_ADC_CR2_JEXTSEL_MASK 15
-#define STM_ADC_CR2_ALIGN 11
-#define STM_ADC_CR2_EOCS 10
-#define STM_ADC_CR2_DDS 9
-#define STM_ADC_CR2_DMA 8
-#define STM_ADC_CR2_DELS 4
-#define STM_ADC_CR2_DELS_NONE 0
-#define STM_ADC_CR2_DELS_UNTIL_READ 1
-#define STM_ADC_CR2_DELS_7 2
-#define STM_ADC_CR2_DELS_15 3
-#define STM_ADC_CR2_DELS_31 4
-#define STM_ADC_CR2_DELS_63 5
-#define STM_ADC_CR2_DELS_127 6
-#define STM_ADC_CR2_DELS_255 7
-#define STM_ADC_CR2_DELS_MASK 7
-#define STM_ADC_CR2_CONT 1
-#define STM_ADC_CR2_ADON 0
-
-#define STM_ADC_CCR_TSVREFE 23
-#define STM_ADC_CCR_ADCPRE 16
-#define STM_ADC_CCR_ADCPRE_HSI_1 0
-#define STM_ADC_CCR_ADCPRE_HSI_2 1
-#define STM_ADC_CCR_ADCPRE_HSI_4 2
-#define STM_ADC_CCR_ADCPRE_MASK 3
-
-struct stm_temp_cal {
- uint16_t vref;
- uint16_t ts_cal_cold;
- uint16_t reserved;
- uint16_t ts_cal_hot;
+#define stm_adc (*(struct stm_adc *) 0x40012400)
+
+#define STM_ADC_ISR_AWD 7
+#define STM_ADC_ISR_OVR 4
+#define STM_ADC_ISR_EOSEQ 3
+#define STM_ADC_ISR_EOC 2
+#define STM_ADC_ISR_EOSMP 1
+#define STM_ADC_ISR_ADRDY 0
+
+#define STM_ADC_IER_AWDIE 7
+#define STM_ADC_IER_OVRIE 4
+#define STM_ADC_IER_EOSEQIE 3
+#define STM_ADC_IER_EOCIE 2
+#define STM_ADC_IER_EOSMPIE 1
+#define STM_ADC_IER_ADRDYIE 0
+
+#define STM_ADC_CR_ADCAL 31
+#define STM_ADC_CR_ADVREGEN 28
+#define STM_ADC_CR_ADSTP 4
+#define STM_ADC_CR_ADSTART 2
+#define STM_ADC_CR_ADDIS 1
+#define STM_ADC_CR_ADEN 0
+
+#define STM_ADC_CFGR1_AWDCH 26
+#define STM_ADC_CFGR1_AWDEN 23
+#define STM_ADC_CFGR1_AWDSGL 22
+#define STM_ADC_CFGR1_DISCEN 16
+#define STM_ADC_CFGR1_AUTOOFF 15
+#define STM_ADC_CFGR1_WAIT 14
+#define STM_ADC_CFGR1_CONT 13
+#define STM_ADC_CFGR1_OVRMOD 12
+#define STM_ADC_CFGR1_EXTEN 10
+#define STM_ADC_CFGR1_EXTEN_DISABLE 0
+#define STM_ADC_CFGR1_EXTEN_RISING 1
+#define STM_ADC_CFGR1_EXTEN_FALLING 2
+#define STM_ADC_CFGR1_EXTEN_BOTH 3
+#define STM_ADC_CFGR1_EXTEN_MASK 3UL
+
+#define STM_ADC_CFGR1_EXTSEL 6
+#define STM_ADC_CFGR1_ALIGN 5
+#define STM_ADC_CFGR1_RES 3
+#define STM_ADC_CFGR1_RES_12 0
+#define STM_ADC_CFGR1_RES_10 1
+#define STM_ADC_CFGR1_RES_8 2
+#define STM_ADC_CFGR1_RES_6 3
+#define STM_ADC_CFGR1_RES_MASK 3UL
+#define STM_ADC_CFGR1_SCANDIR 2
+#define STM_ADC_CFGR1_SCANDIR_UP 0
+#define STM_ADC_CFGR1_SCANDIR_DOWN 1
+#define STM_ADC_CFGR1_DMACFG 1
+#define STM_ADC_CFGR1_DMACFG_ONESHOT 0
+#define STM_ADC_CFGR1_DMACFG_CIRCULAR 1
+#define STM_ADC_CFGR1_DMAEN 0
+
+#define STM_ADC_CFGR2_CKMODE 30
+#define STM_ADC_CFGR2_CKMODE_ADCCLK 0
+#define STM_ADC_CFGR2_CKMODE_PCLK_2 1
+#define STM_ADC_CFGR2_CKMODE_PCLK_4 2
+#define STM_ADC_CFGR2_CKMODE_PCLK 3
+
+#define STM_ADC_SMPR_SMP 0
+#define STM_ADC_SMPR_SMP_1_5 0
+#define STM_ADC_SMPR_SMP_7_5 1
+#define STM_ADC_SMPR_SMP_13_5 2
+#define STM_ADC_SMPR_SMP_28_5 3
+#define STM_ADC_SMPR_SMP_41_5 4
+#define STM_ADC_SMPR_SMP_55_5 5
+#define STM_ADC_SMPR_SMP_71_5 6
+#define STM_ADC_SMPR_SMP_239_5 7
+
+#define STM_ADC_TR_HT 16
+#define STM_ADC_TR_LT 0
+
+#define STM_ADC_CCR_LFMEN 25
+#define STM_ADC_CCR_VLCDEN 24
+#define STM_ADC_CCR_TSEN 23
+#define STM_ADC_CCR_VREFEN 22
+#define STM_ADC_CCR_PRESC 18
+
+#define STM_ADC_CHSEL_TEMP 18
+#define STM_ADC_CHSEL_VREF 17
+#define STM_ADC_CHSEL_VLCD 16
+
+struct stm_cal {
+ uint16_t ts_cal_cold; /* 30°C */
+ uint16_t vrefint_cal;
+ uint16_t unused_c0;
+ uint16_t ts_cal_hot; /* 110°C */
};
-extern struct stm_temp_cal stm_temp_cal;
+extern struct stm_cal stm_cal;
-#define stm_temp_cal_cold 25
+#define stm_temp_cal_cold 30
#define stm_temp_cal_hot 110
struct stm_dbg_mcu {
extern uint32_t
stm_flash_size(void);
-struct stm_unique_id {
- uint32_t u_id0;
- uint32_t u_id1;
- uint32_t u_id2;
-};
-
-extern struct stm_unique_id stm_unique_id;
-#define stm_unique_id (*((struct stm_unique_id) 0x1ff80050))
-
struct stm_device_id {
- uint32_t device_id;
+ char lot_num_4_6[3];
+ uint8_t waf_num;
+ char lot_num_0_3[4];
+ uint8_t unique_id[4];
};
extern struct stm_device_id stm_device_id;
-#define stm_device_id (*((struct stm_device_id) 0x40015800))
+#define stm_device_id (*((struct stm_device_id *) 0x1ff80050))
#define STM_NUM_I2C 2
#define STM_I2C_CR2_FREQ_16_MHZ 16
#define STM_I2C_CR2_FREQ_24_MHZ 24
#define STM_I2C_CR2_FREQ_32_MHZ 32
-#define STM_I2C_CR2_FREQ_MASK 0x3f
+#define STM_I2C_CR2_FREQ_MASK 0x3fUL
#define STM_I2C_SR1_SMBALERT 15
#define STM_I2C_SR1_TIMEOUT 14
#define STM_I2C_SR1_SB 0
#define STM_I2C_SR2_PEC 8
-#define STM_I2C_SR2_PEC_MASK 0xff00
+#define STM_I2C_SR2_PEC_MASK 0xff00UL
#define STM_I2C_SR2_DUALF 7
#define STM_I2C_SR2_SMBHOST 6
#define STM_I2C_SR2_SMBDEFAULT 5
#define STM_I2C_CCR_FS 15
#define STM_I2C_CCR_DUTY 14
#define STM_I2C_CCR_CCR 0
-#define STM_I2C_CCR_MASK 0x7ff
+#define STM_I2C_CCR_MASK 0x7ffUL
struct stm_tim234 {
vuint32_t cr1;
#define STM_TIM234_CR1_CKD_1 0
#define STM_TIM234_CR1_CKD_2 1
#define STM_TIM234_CR1_CKD_4 2
-#define STM_TIM234_CR1_CKD_MASK 3
+#define STM_TIM234_CR1_CKD_MASK 3UL
#define STM_TIM234_CR1_ARPE 7
#define STM_TIM234_CR1_CMS 5
#define STM_TIM234_CR1_CMS_EDGE 0
#define STM_TIM234_CR1_CMS_CENTER_1 1
#define STM_TIM234_CR1_CMS_CENTER_2 2
#define STM_TIM234_CR1_CMS_CENTER_3 3
-#define STM_TIM234_CR1_CMS_MASK 3
+#define STM_TIM234_CR1_CMS_MASK 3UL
#define STM_TIM234_CR1_DIR 4
#define STM_TIM234_CR1_DIR_UP 0
#define STM_TIM234_CR1_DIR_DOWN 1
#define STM_TIM234_CR2_MMS_COMPARE_OC2REF 5
#define STM_TIM234_CR2_MMS_COMPARE_OC3REF 6
#define STM_TIM234_CR2_MMS_COMPARE_OC4REF 7
-#define STM_TIM234_CR2_MMS_MASK 7
+#define STM_TIM234_CR2_MMS_MASK 7UL
#define STM_TIM234_CR2_CCDS 3
#define STM_TIM234_SMCR_ETP 15
#define STM_TIM234_SMCR_ETPS_DIV_2 1
#define STM_TIM234_SMCR_ETPS_DIV_4 2
#define STM_TIM234_SMCR_ETPS_DIV_8 3
-#define STM_TIM234_SMCR_ETPS_MASK 3
+#define STM_TIM234_SMCR_ETPS_MASK 3UL
#define STM_TIM234_SMCR_ETF 8
#define STM_TIM234_SMCR_ETF_NONE 0
#define STM_TIM234_SMCR_ETF_INT_N_2 1
#define STM_TIM234_SMCR_ETF_DTS_32_N_5 13
#define STM_TIM234_SMCR_ETF_DTS_32_N_6 14
#define STM_TIM234_SMCR_ETF_DTS_32_N_8 15
-#define STM_TIM234_SMCR_ETF_MASK 15
+#define STM_TIM234_SMCR_ETF_MASK 15UL
#define STM_TIM234_SMCR_MSM 7
#define STM_TIM234_SMCR_TS 4
#define STM_TIM234_SMCR_TS_ITR0 0
#define STM_TIM234_SMCR_TS_TI1FP1 5
#define STM_TIM234_SMCR_TS_TI2FP2 6
#define STM_TIM234_SMCR_TS_ETRF 7
-#define STM_TIM234_SMCR_TS_MASK 7
+#define STM_TIM234_SMCR_TS_MASK 7UL
#define STM_TIM234_SMCR_OCCS 3
#define STM_TIM234_SMCR_SMS 0
#define STM_TIM234_SMCR_SMS_DISABLE 0
#define STM_TIM234_SMCR_SMS_GATED_MODE 5
#define STM_TIM234_SMCR_SMS_TRIGGER_MODE 6
#define STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK 7
-#define STM_TIM234_SMCR_SMS_MASK 7
+#define STM_TIM234_SMCR_SMS_MASK 7UL
#define STM_TIM234_DIER_TDE 14
#define STM_TIM234_DIER_CC4DE 12
#define STM_TIM234_CCMR1_OC2M_FORCE_HIGH 5
#define STM_TIM234_CCMR1_OC2M_PWM_MODE_1 6
#define STM_TIM234_CCMR1_OC2M_PWM_MODE_2 7
-#define STM_TIM234_CCMR1_OC2M_MASK 7
+#define STM_TIM234_CCMR1_OC2M_MASK 7UL
#define STM_TIM234_CCMR1_OC2PE 11
#define STM_TIM234_CCMR1_OC2FE 10
#define STM_TIM234_CCMR1_CC2S 8
#define STM_TIM234_CCMR1_CC2S_INPUT_TI2 1
#define STM_TIM234_CCMR1_CC2S_INPUT_TI1 2
#define STM_TIM234_CCMR1_CC2S_INPUT_TRC 3
-#define STM_TIM234_CCMR1_CC2S_MASK 3
+#define STM_TIM234_CCMR1_CC2S_MASK 3UL
#define STM_TIM234_CCMR1_OC1CE 7
#define STM_TIM234_CCMR1_OC1M 4
#define STM_TIM234_CCMR1_OC1M_FORCE_HIGH 5
#define STM_TIM234_CCMR1_OC1M_PWM_MODE_1 6
#define STM_TIM234_CCMR1_OC1M_PWM_MODE_2 7
-#define STM_TIM234_CCMR1_OC1M_MASK 7
+#define STM_TIM234_CCMR1_OC1M_MASK 7UL
#define STM_TIM234_CCMR1_OC1PE 3
#define STM_TIM234_CCMR1_OC1FE 2
#define STM_TIM234_CCMR1_CC1S 0
#define STM_TIM234_CCMR1_CC1S_INPUT_TI1 1
#define STM_TIM234_CCMR1_CC1S_INPUT_TI2 2
#define STM_TIM234_CCMR1_CC1S_INPUT_TRC 3
-#define STM_TIM234_CCMR1_CC1S_MASK 3
+#define STM_TIM234_CCMR1_CC1S_MASK 3UL
#define STM_TIM234_CCMR1_IC2F 12
#define STM_TIM234_CCMR1_IC2F_NONE 0
#define STM_TIM234_CCMR2_OC4M_FORCE_HIGH 5
#define STM_TIM234_CCMR2_OC4M_PWM_MODE_1 6
#define STM_TIM234_CCMR2_OC4M_PWM_MODE_2 7
-#define STM_TIM234_CCMR2_OC4M_MASK 7
+#define STM_TIM234_CCMR2_OC4M_MASK 7UL
#define STM_TIM234_CCMR2_OC4PE 11
#define STM_TIM234_CCMR2_OC4FE 10
#define STM_TIM234_CCMR2_CC4S 8
#define STM_TIM234_CCMR2_CC4S_INPUT_TI4 1
#define STM_TIM234_CCMR2_CC4S_INPUT_TI3 2
#define STM_TIM234_CCMR2_CC4S_INPUT_TRC 3
-#define STM_TIM234_CCMR2_CC4S_MASK 3
+#define STM_TIM234_CCMR2_CC4S_MASK 3UL
#define STM_TIM234_CCMR2_OC3CE 7
#define STM_TIM234_CCMR2_OC3M 4
#define STM_TIM234_CCMR2_OC3M_FORCE_HIGH 5
#define STM_TIM234_CCMR2_OC3M_PWM_MODE_1 6
#define STM_TIM234_CCMR2_OC3M_PWM_MODE_2 7
-#define STM_TIM234_CCMR2_OC3M_MASK 7
+#define STM_TIM234_CCMR2_OC3M_MASK 7UL
#define STM_TIM234_CCMR2_OC3PE 3
#define STM_TIM234_CCMR2_OC3FE 2
#define STM_TIM234_CCMR2_CC3S 0
#define STM_TIM234_CCMR2_CC3S_INPUT_TI3 1
#define STM_TIM234_CCMR2_CC3S_INPUT_TI4 2
#define STM_TIM234_CCMR2_CC3S_INPUT_TRC 3
-#define STM_TIM234_CCMR2_CC3S_MASK 3
+#define STM_TIM234_CCMR2_CC3S_MASK 3UL
#define STM_TIM234_CCER_CC4NP 15
#define STM_TIM234_CCER_CC4P 13
#define STM_TIM234_CCER_CC1P_ACTIVE_LOW 1
#define STM_TIM234_CCER_CC1E 0
-struct stm_usb {
- vuint32_t epr[8];
- uint8_t reserved_20[0x40 - 0x20];
- vuint32_t cntr;
- vuint32_t istr;
- vuint32_t fnr;
- vuint32_t daddr;
- vuint32_t btable;
-};
-
-#define STM_USB_EPR_CTR_RX 15
-#define STM_USB_EPR_CTR_RX_WRITE_INVARIANT 1
-#define STM_USB_EPR_DTOG_RX 14
-#define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT 0
-#define STM_USB_EPR_STAT_RX 12
-#define STM_USB_EPR_STAT_RX_DISABLED 0
-#define STM_USB_EPR_STAT_RX_STALL 1
-#define STM_USB_EPR_STAT_RX_NAK 2
-#define STM_USB_EPR_STAT_RX_VALID 3
-#define STM_USB_EPR_STAT_RX_MASK 3
-#define STM_USB_EPR_STAT_RX_WRITE_INVARIANT 0
-#define STM_USB_EPR_SETUP 11
-#define STM_USB_EPR_EP_TYPE 9
-#define STM_USB_EPR_EP_TYPE_BULK 0
-#define STM_USB_EPR_EP_TYPE_CONTROL 1
-#define STM_USB_EPR_EP_TYPE_ISO 2
-#define STM_USB_EPR_EP_TYPE_INTERRUPT 3
-#define STM_USB_EPR_EP_TYPE_MASK 3
-#define STM_USB_EPR_EP_KIND 8
-#define STM_USB_EPR_EP_KIND_DBL_BUF 1 /* Bulk */
-#define STM_USB_EPR_EP_KIND_STATUS_OUT 1 /* Control */
-#define STM_USB_EPR_CTR_TX 7
-#define STM_USB_CTR_TX_WRITE_INVARIANT 1
-#define STM_USB_EPR_DTOG_TX 6
-#define STM_USB_EPR_DTOG_TX_WRITE_INVARIANT 0
-#define STM_USB_EPR_STAT_TX 4
-#define STM_USB_EPR_STAT_TX_DISABLED 0
-#define STM_USB_EPR_STAT_TX_STALL 1
-#define STM_USB_EPR_STAT_TX_NAK 2
-#define STM_USB_EPR_STAT_TX_VALID 3
-#define STM_USB_EPR_STAT_TX_WRITE_INVARIANT 0
-#define STM_USB_EPR_STAT_TX_MASK 3
-#define STM_USB_EPR_EA 0
-#define STM_USB_EPR_EA_MASK 0xf
-
-#define STM_USB_CNTR_CTRM 15
-#define STM_USB_CNTR_PMAOVRM 14
-#define STM_USB_CNTR_ERRM 13
-#define STM_USB_CNTR_WKUPM 12
-#define STM_USB_CNTR_SUSPM 11
-#define STM_USB_CNTR_RESETM 10
-#define STM_USB_CNTR_SOFM 9
-#define STM_USB_CNTR_ESOFM 8
-#define STM_USB_CNTR_RESUME 4
-#define STM_USB_CNTR_FSUSP 3
-#define STM_USB_CNTR_LP_MODE 2
-#define STM_USB_CNTR_PDWN 1
-#define STM_USB_CNTR_FRES 0
-
-#define STM_USB_ISTR_CTR 15
-#define STM_USB_ISTR_PMAOVR 14
-#define STM_USB_ISTR_ERR 13
-#define STM_USB_ISTR_WKUP 12
-#define STM_USB_ISTR_SUSP 11
-#define STM_USB_ISTR_RESET 10
-#define STM_USB_ISTR_SOF 9
-#define STM_USB_ISTR_ESOF 8
-#define STM_USB_ISTR_DIR 4
-#define STM_USB_ISTR_EP_ID 0
-#define STM_USB_ISTR_EP_ID_MASK 0xf
-
-#define STM_USB_FNR_RXDP 15
-#define STM_USB_FNR_RXDM 14
-#define STM_USB_FNR_LCK 13
-#define STM_USB_FNR_LSOF 11
-#define STM_USB_FNR_LSOF_MASK 0x3
-#define STM_USB_FNR_FN 0
-#define STM_USB_FNR_FN_MASK 0x7ff
-
-#define STM_USB_DADDR_EF 7
-#define STM_USB_DADDR_ADD 0
-#define STM_USB_DADDR_ADD_MASK 0x7f
-
-extern struct stm_usb stm_usb;
-
-union stm_usb_bdt {
- struct {
- vuint32_t addr_tx;
- vuint32_t count_tx;
- vuint32_t addr_rx;
- vuint32_t count_rx;
- } single;
- struct {
- vuint32_t addr;
- vuint32_t count;
- } double_tx[2];
- struct {
- vuint32_t addr;
- vuint32_t count;
- } double_rx[2];
-};
-
-#define STM_USB_BDT_COUNT_RX_BL_SIZE 15
-#define STM_USB_BDT_COUNT_RX_NUM_BLOCK 10
-#define STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK 0x1f
-#define STM_USB_BDT_COUNT_RX_COUNT_RX 0
-#define STM_USB_BDT_COUNT_RX_COUNT_RX_MASK 0x1ff
-
-#define STM_USB_BDT_SIZE 8
-
-extern uint8_t stm_usb_sram[] __attribute__ ((aligned(4)));
-
struct stm_exti {
vuint32_t imr;
vuint32_t emr;
};
extern struct stm_exti stm_exti;
+#define stm_exti (*(struct stm_exti *) 0x40010400)
+
+struct stm_vrefint_cal {
+ vuint16_t vrefint_cal;
+};
+
+extern struct stm_vrefint_cal stm_vrefint_cal;
+#define stm_vrefint_cal (*(struct stm_vrefint_cal *) 0x1ff80078)
+
+/* Flash interface */
+
+struct stm_flash {
+ vuint32_t acr;
+ vuint32_t pecr;
+ vuint32_t pdkeyr;
+ vuint32_t pekeyr;
+
+ vuint32_t prgkeyr;
+ vuint32_t optkeyr;
+ vuint32_t sr;
+ vuint32_t obr;
+
+ vuint32_t wrpr;
+};
+
+
+extern uint32_t __storage[], __storage_size[];
+
+#define STM_FLASH_PAGE_SIZE 128
+
+#define ao_storage_unit 128
+#define ao_storage_total ((uintptr_t) __storage_size)
+#define ao_storage_block STM_FLASH_PAGE_SIZE
+#define AO_STORAGE_ERASED_BYTE 0x00
+
+extern struct stm_flash stm_flash;
+
+#define STM_FLASH_ACR_PRE_READ (6)
+#define STM_FLASH_ACR_DISAB_BUF (5)
+#define STM_FLASH_ACR_RUN_PD (4)
+#define STM_FLASH_ACR_SLEEP_PD (3)
+#define STM_FLASH_ACR_PRFEN (1)
+#define STM_FLASH_ACR_LATENCY (0)
+
+#define STM_FLASH_PECR_NZDISABLE 23
+#define STM_FLASH_PECR_OBL_LAUNCH 18
+#define STM_FLASH_PECR_ERRIE 17
+#define STM_FLASH_PECR_EOPIE 16
+#define STM_FLASH_PECR_PARRALELLBANK 15
+#define STM_FLASH_PECR_FPRG 10
+#define STM_FLASH_PECR_ERASE 9
+#define STM_FLASH_PECR_FIX 8
+#define STM_FLASH_PECR_DATA 4
+#define STM_FLASH_PECR_PROG 3
+#define STM_FLASH_PECR_OPT_LOCK 2
+#define STM_FLASH_PECR_PRG_LOCK 1
+#define STM_FLASH_PECR_PE_LOCK 0
+
+#define STM_FLASH_SR_OPTVERR 11
+#define STM_FLASH_SR_SIZERR 10
+#define STM_FLASH_SR_PGAERR 9
+#define STM_FLASH_SR_WRPERR 8
+#define STM_FLASH_SR_READY 3
+#define STM_FLASH_SR_ENDHV 2
+#define STM_FLASH_SR_EOP 1
+#define STM_FLASH_SR_BSY 0
+
+#define STM_FLASH_OPTKEYR_OPTKEY1 0xFBEAD9C8
+#define STM_FLASH_OPTKEYR_OPTKEY2 0x24252627
+
+#define STM_FLASH_PEKEYR_PEKEY1 0x89ABCDEF
+#define STM_FLASH_PEKEYR_PEKEY2 0x02030405
+
+#define STM_FLASH_PRGKEYR_PRGKEY1 0x8C9DAEBF
+#define STM_FLASH_PRGKEYR_PRGKEY2 0x13141516
#endif /* _STM32L0_H_ */