#define STM_RCC_PLLCFGR_PLLN 6
#define STM_RCC_PLLCFGR_PLLN_MASK 0x1ff
#define STM_RCC_PLLCFGR_PLLP 16
+#define STM_RCC_PLLCFGR_PLLP_DIV_2 0
+#define STM_RCC_PLLCFGR_PLLP_DIV_4 1
+#define STM_RCC_PLLCFGR_PLLP_DIV_6 2
+#define STM_RCC_PLLCFGR_PLLP_DIV_8 3
#define STM_RCC_PLLCFGR_PLLP_MASK 0x3
#define STM_RCC_PLLCFGR_PLLSRC 22
#define STM_RCC_PLLCFGR_PLLSRC_HSI 0