#ifdef AO_BOOT_CHAIN
if (ao_boot_check_chain()) {
#ifdef AO_BOOT_PIN
- ao_boot_check_pin();
+ if (ao_boot_check_pin())
#endif
+ {
+ ao_boot_chain(AO_BOOT_APPLICATION_BASE);
+ }
}
#endif
/* Enable FPU */
i(0xe8, otg_fs_wkup),
i(0xec, tim8_brk_tim12),
i(0xf0, tim8_up_tim13),
+ i(0xf4, tim8_trg_com_tim14),
+ i(0xf8, tim8_cc),
+ i(0xfc, dma1_stream7),
+ i(0x100, fsmc),
+ i(0x104, sdio),
+ i(0x108, tim5),
+ i(0x10c, spi3),
+ i(0x110, uart4),
+ i(0x114, uart5),
+ i(0x118,tim6_glb_it),
+ i(0x11c, tim7),
+ i(0x120, dma2_stream0),
+ i(0x124, dma2_stream1),
+ i(0x128, dma2_stream2),
+ i(0x12c, dma2_stream3),
+ i(0x130, dma2_stream4),
+ i(0x134, dfsdm1_flt0),
+ i(0x138, dfsdm1_flt1),
+ i(0x13c, can2_tx),
+ i(0x140, can2_rx0),
+ i(0x144, can2_rx1),
+ i(0x148, can2_sce),
+ i(0x14c, otg_fs),
+ i(0x150, dma2_stream5),
+ i(0x154, dma2_stream6),
+ i(0x158, dma2_stream7),
i(0x15c, usart6),
+ i(0x160, i2c3_ev),
+ i(0x164, i2c3_er),
+ i(0x168, can3_tx),
+ i(0x16c, can3_rx0),
+ i(0x170, can3_rx1),
+ i(0x174, can3_sce),
+ i(0x17c, crypto),
+ i(0x180, rng),
+ i(0x184, fpu),
+ i(0x188, uart7),
+ i(0x18c, uart8),
+ i(0x190, spi4),
+ i(0x194, spi5),
+ i(0x19c, sai1),
+ i(0x1a0, uart9),
+ i(0x1a4, uart10),
+ i(0x1b0, quad_spi),
+ i(0x1bc, i2cfmp1_ev),
+ i(0x1c0, i2cfmp1_er),
+ i(0x1c4, exti23),
+ i(0x1c8, dfsdm2_flt0),
+ i(0x1cc, dfsdm2_flt1),
+ i(0x1d0, dfsdm2_flt2),
+ i(0x1d4, dfsdm2_flt3),
};