#define STM_RCC_CR_HSIRDY (1)
#define STM_RCC_CR_HSION (0)
-#define STM_RCC_CFGR_MCOPRE (28)
-#define STM_RCC_CFGR_MCOPRE_DIV_1 0
-#define STM_RCC_CFGR_MCOPRE_DIV_2 1
-#define STM_RCC_CFGR_MCOPRE_DIV_4 2
-#define STM_RCC_CFGR_MCOPRE_DIV_8 3
-#define STM_RCC_CFGR_MCOPRE_DIV_16 4
-#define STM_RCC_CFGR_MCOPRE_MASK 7UL
-
#define STM_RCC_CFGR_MCO (24)
#define STM_RCC_CFGR_MCO_DISABLE 0
#define STM_RCC_CFGR_MCO_SYSCLK 4
#define STM_RCC_CFGR_PLLXTPRE (17)
#define STM_RCC_CFGR_PLLXTPRE_1 0
#define STM_RCC_CFGR_PLLXTPRE_2 1
+#define STM_RCC_CFGR_PLLXTPRE_MASK 1UL
#define STM_RCC_CFGR_PLLSRC (16)
#define STM_RCC_CFGR_PLLSRC_HSI_2 0
#define STM_RCC_CFGR_ADCPRE_4 1
#define STM_RCC_CFGR_ADCPRE_6 2
#define STM_RCC_CFGR_ADCPRE_8 3
+#define STM_RCC_CFGR_ADCPRE_MASK 3UL
#define STM_RCC_CFGR_PPRE2 (11)
#define STM_RCC_CFGR_PPRE2_DIV_1 0
#define stm_afio (*((struct stm_afio *) 0x40010000))
+#define STM_AFIO_MAPR_SWJ_CFG 24
+#define STM_AFIO_MAPR_SWJ_CFG_FULL_SWJ 0
+#define STM_AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJTRST 1
+#define STM_AFIO_MAPR_SWJ_CFG_SW_DP 2
+#define STM_AFIO_MAPR_SWJ_CFG_DISABLE 4
+#define STM_AFIO_MAPR_SWJ_CFG_MASK 7UL
#define STM_AFIO_MAPR_ADC2_ETRGREG_REMAP 20
#define STM_AFIO_MAPR_ADC2_ETRGINJ_REMAP 19
#define STM_AFIO_MAPR_ADC1_ETRGREG_REMAP 18
vuint32_t dr;
};
-extern struct stm_adc stm_adc;
+extern struct stm_adc stm_adc1;
-#define stm_adc (*((struct stm_adc *) 0x40012400))
+//#define stm_adc1 (*((struct stm_adc *) 0x40012400))
#define STM_ADC_SQ_TEMP 16
#define STM_ADC_SQ_V_REF 17
#define STM_ADC_CR1_AWDCH_MASK 0x1fUL
#define STM_ADC_CR2_TSVREF 23
-#define STM_ADC_CR2_SWSTART 21
+#define STM_ADC_CR2_SWSTART 22
#define STM_ADC_CR2_JWSTART 21
#define STM_ADC_CR2_EXTTRIG 20
#define STM_ADC_CR2_EXTSEL 17
uint8_t shift = (pin & 3) << 2;
uint8_t val = 0;
- /* Enable AFIO */
- stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_AFIOEN);
-
if (gpio == &stm_gpioa)
val = STM_AFIO_EXTICR_PA;
else if (gpio == &stm_gpiob)