#define STM_RCC_CFGR_ADCPRE_4 1
#define STM_RCC_CFGR_ADCPRE_6 2
#define STM_RCC_CFGR_ADCPRE_8 3
+#define STM_RCC_CFGR_ADCPRE_MASK 3UL
#define STM_RCC_CFGR_PPRE2 (11)
#define STM_RCC_CFGR_PPRE2_DIV_1 0
#define STM_RCC_APB1ENR_SPI3EN 15
#define STM_RCC_APB1ENR_SPI2EN 14
#define STM_RCC_APB1ENR_WWDGEN 11
-#define STM_RCC_APB1ENR_TIM14EN 8
-#define STM_RCC_APB1ENR_TIM13EN 7
-#define STM_RCC_APB1ENR_TIM12EN 6
#define STM_RCC_APB1ENR_TIM7EN 5
#define STM_RCC_APB1ENR_TIM6EN 4
#define STM_RCC_APB1ENR_TIM5EN 3
#define stm_afio (*((struct stm_afio *) 0x40010000))
+#define STM_AFIO_MAPR_SWJ_CFG 24
+#define STM_AFIO_MAPR_SWJ_CFG_FULL_SWJ 0
+#define STM_AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJTRST 1
+#define STM_AFIO_MAPR_SWJ_CFG_SW_DP 2
+#define STM_AFIO_MAPR_SWJ_CFG_DISABLE 4
+#define STM_AFIO_MAPR_SWJ_CFG_MASK 7UL
#define STM_AFIO_MAPR_ADC2_ETRGREG_REMAP 20
#define STM_AFIO_MAPR_ADC2_ETRGINJ_REMAP 19
#define STM_AFIO_MAPR_ADC1_ETRGREG_REMAP 18
#define STM_AFIO_MAPR_CAN_REMAP_PA11_PA12 0
#define STM_AFIO_MAPR_CAN_REMAP_PB8_PB9 2
#define STM_AFIO_MAPR_CAN_REMAP_PD0_PD1 3
-#define STM_AFIO_MAPR_CAN_REMAP_MASK 3
+#define STM_AFIO_MAPR_CAN_REMAP_MASK 3UL
#define STM_AFIO_MAPR_TIM4_REMAP 12
#define STM_AFIO_MAPR_TIM3_REMAP 10
#define STM_AFIO_MAPR_TIM3_REMAP_PA6_PA7_PB0_PB1 0
#define STM_AFIO_MAPR_TIM3_REMAP_PB4_PB5_PB0_PB1 2
#define STM_AFIO_MAPR_TIM3_REMAP_PC6_PC7_PC8_PC9 3
-#define STM_AFIO_MAPR_TIM3_REMAP_MASK 3
+#define STM_AFIO_MAPR_TIM3_REMAP_MASK 3UL
#define STM_AFIO_MAPR_TIM2_REMAP 8
#define STM_AFIO_MAPR_TIM2_REMAP_PA0_PA1_PA2_PA3 0
#define STM_AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3 1
#define STM_AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11 2
#define STM_AFIO_MAPR_TIM2_REMAP_PA15_PB3_PB10_PB11 3
-#define STM_AFIO_MAPR_TIM2_REMAP_MASK 3
+#define STM_AFIO_MAPR_TIM2_REMAP_MASK 3UL
#define STM_AFIO_MAPR_TIM1_REMAP 6
#define STM_AFIO_MAPR_TIM1_REMAP_PA12_PA8_PA9_PA10_PA11_PB12_PB13_PB14_PB15 0
#define STM_AFIO_MAPR_TIM1_REMAP_PA12_PA8_PA9_PA10_PA11_PA6_PA7_PB0_PB1 1
vuint32_t dr;
};
-extern struct stm_adc stm_adc;
+extern struct stm_adc stm_adc1;
-#define stm_adc (*((struct stm_adc *) 0x40012400))
+//#define stm_adc1 (*((struct stm_adc *) 0x40012400))
#define STM_ADC_SQ_TEMP 16
#define STM_ADC_SQ_V_REF 17
#define STM_ADC_CR1_AWDCH_MASK 0x1fUL
#define STM_ADC_CR2_TSVREF 23
-#define STM_ADC_CR2_SWSTART 21
+#define STM_ADC_CR2_SWSTART 22
#define STM_ADC_CR2_JWSTART 21
#define STM_ADC_CR2_EXTTRIG 20
#define STM_ADC_CR2_EXTSEL 17
uint8_t shift = (pin & 3) << 2;
uint8_t val = 0;
- /* Enable AFIO */
- stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_AFIOEN);
-
if (gpio == &stm_gpioa)
val = STM_AFIO_EXTICR_PA;
else if (gpio == &stm_gpiob)