#define STM_RCC_CR_HSIRDY (1)
#define STM_RCC_CR_HSION (0)
-#define STM_RCC_CFGR_MCOPRE (28)
-#define STM_RCC_CFGR_MCOPRE_DIV_1 0
-#define STM_RCC_CFGR_MCOPRE_DIV_2 1
-#define STM_RCC_CFGR_MCOPRE_DIV_4 2
-#define STM_RCC_CFGR_MCOPRE_DIV_8 3
-#define STM_RCC_CFGR_MCOPRE_DIV_16 4
-#define STM_RCC_CFGR_MCOPRE_MASK 7UL
-
#define STM_RCC_CFGR_MCO (24)
#define STM_RCC_CFGR_MCO_DISABLE 0
#define STM_RCC_CFGR_MCO_SYSCLK 4
#define STM_RCC_CFGR_PLLXTPRE (17)
#define STM_RCC_CFGR_PLLXTPRE_1 0
#define STM_RCC_CFGR_PLLXTPRE_2 1
+#define STM_RCC_CFGR_PLLXTPRE_MASK 1UL
#define STM_RCC_CFGR_PLLSRC (16)
#define STM_RCC_CFGR_PLLSRC_HSI_2 0
#define STM_RCC_CFGR_ADCPRE_4 1
#define STM_RCC_CFGR_ADCPRE_6 2
#define STM_RCC_CFGR_ADCPRE_8 3
+#define STM_RCC_CFGR_ADCPRE_MASK 3UL
#define STM_RCC_CFGR_PPRE2 (11)
#define STM_RCC_CFGR_PPRE2_DIV_1 0
#define STM_RCC_APB1ENR_SPI3EN 15
#define STM_RCC_APB1ENR_SPI2EN 14
#define STM_RCC_APB1ENR_WWDGEN 11
-#define STM_RCC_APB1ENR_TIM14EN 8
-#define STM_RCC_APB1ENR_TIM13EN 7
-#define STM_RCC_APB1ENR_TIM12EN 6
#define STM_RCC_APB1ENR_TIM7EN 5
#define STM_RCC_APB1ENR_TIM6EN 4
#define STM_RCC_APB1ENR_TIM5EN 3
#define STM_SCB_AIRCR_VECTCLRACTIVE 1
#define STM_SCB_AIRCR_VECTRESET 0
+struct stm_dbgmcu {
+ uint32_t idcode;
+};
+
+extern struct stm_dbgmcu stm_dbgmcu;
+
+static inline uint16_t
+stm_dev_id(void) {
+ return stm_dbgmcu.idcode & 0xfff;
+}
+
struct stm_flash {
vuint32_t acr;
vuint32_t keyr;
#define STM_FLASH_CR_PG 0
#define STM_FLASH_RDPRT_KEY 0x00A5
-#define STM_FLASH_FPEC_KEY1 0x45670123
-#define STM_FLASH_FPEC_KEY2 0xCDEF89AB
+#define STM_FLASH_KEYR_KEY1 0x45670123
+#define STM_FLASH_KEYR_KEY2 0xCDEF89AB
struct stm_flash_data {
extern struct stm_gpio stm_gpiod;
extern struct stm_gpio stm_gpioe;
-//#define stm_gpioe (*((struct stm_gpio *) 0x40011800))
-//#define stm_gpiod (*((struct stm_gpio *) 0x40011400))
-//#define stm_gpioc (*((struct stm_gpio *) 0x40011000))
-//#define stm_gpiob (*((struct stm_gpio *) 0x40010c00))
-//#define stm_gpioa (*((struct stm_gpio *) 0x40010800))
+#define stm_gpioe (*((struct stm_gpio *) 0x40011800))
+#define stm_gpiod (*((struct stm_gpio *) 0x40011400))
+#define stm_gpioc (*((struct stm_gpio *) 0x40011000))
+#define stm_gpiob (*((struct stm_gpio *) 0x40010c00))
+#define stm_gpioa (*((struct stm_gpio *) 0x40010800))
struct stm_afio {
vuint32_t evcr;
extern struct stm_afio stm_afio;
-//#define stm_afio (*((struct stm_afio *) 0x40010000))
+#define stm_afio (*((struct stm_afio *) 0x40010000))
+#define STM_AFIO_MAPR_SWJ_CFG 24
+#define STM_AFIO_MAPR_SWJ_CFG_FULL_SWJ 0
+#define STM_AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJTRST 1
+#define STM_AFIO_MAPR_SWJ_CFG_SW_DP 2
+#define STM_AFIO_MAPR_SWJ_CFG_DISABLE 4
+#define STM_AFIO_MAPR_SWJ_CFG_MASK 7UL
#define STM_AFIO_MAPR_ADC2_ETRGREG_REMAP 20
#define STM_AFIO_MAPR_ADC2_ETRGINJ_REMAP 19
#define STM_AFIO_MAPR_ADC1_ETRGREG_REMAP 18
#define STM_AFIO_MAPR_CAN_REMAP_PA11_PA12 0
#define STM_AFIO_MAPR_CAN_REMAP_PB8_PB9 2
#define STM_AFIO_MAPR_CAN_REMAP_PD0_PD1 3
-#define STM_AFIO_MAPR_CAN_REMAP_MASK 3
+#define STM_AFIO_MAPR_CAN_REMAP_MASK 3UL
#define STM_AFIO_MAPR_TIM4_REMAP 12
#define STM_AFIO_MAPR_TIM3_REMAP 10
#define STM_AFIO_MAPR_TIM3_REMAP_PA6_PA7_PB0_PB1 0
#define STM_AFIO_MAPR_TIM3_REMAP_PB4_PB5_PB0_PB1 2
#define STM_AFIO_MAPR_TIM3_REMAP_PC6_PC7_PC8_PC9 3
-#define STM_AFIO_MAPR_TIM3_REMAP_MASK 3
+#define STM_AFIO_MAPR_TIM3_REMAP_MASK 3UL
#define STM_AFIO_MAPR_TIM2_REMAP 8
#define STM_AFIO_MAPR_TIM2_REMAP_PA0_PA1_PA2_PA3 0
#define STM_AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3 1
#define STM_AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11 2
#define STM_AFIO_MAPR_TIM2_REMAP_PA15_PB3_PB10_PB11 3
-#define STM_AFIO_MAPR_TIM2_REMAP_MASK 3
+#define STM_AFIO_MAPR_TIM2_REMAP_MASK 3UL
#define STM_AFIO_MAPR_TIM1_REMAP 6
#define STM_AFIO_MAPR_TIM1_REMAP_PA12_PA8_PA9_PA10_PA11_PB12_PB13_PB14_PB15 0
#define STM_AFIO_MAPR_TIM1_REMAP_PA12_PA8_PA9_PA10_PA11_PA6_PA7_PB0_PB1 1
#define STM_AFIO_MAPR_SPI1_REMAP_PA15_PB3_PB4_PB5 1
#define STM_AFIO_MAPR_SPI1_REMAP_MASK 1
+#define STM_AFIO_EXTICR_PA 0
+#define STM_AFIO_EXTICR_PB 1
+#define STM_AFIO_EXTICR_PC 2
+#define STM_AFIO_EXTICR_PD 3
+#define STM_AFIO_EXTICR_PE 4
+#define STM_AFIO_EXTICR_PF 5
+#define STM_AFIO_EXTICR_PG 6
+
static inline void
stm_set_afio_mapr(uint8_t bit, uint32_t val, uint32_t mask) {
uint32_t mapr = stm_afio.mapr;
extern struct stm_usb stm_usb;
-
-//#define stm_usb (*((struct stm_usb *) 0x40005c00))
+#define stm_usb (*((struct stm_usb *) 0x40005c00))
union stm_usb_bdt {
struct {
extern uint8_t stm_usb_sram[] __attribute__ ((aligned(4)));
-//#define stm_usb_sram ((uint8_t *)0x40006000);
+//#define stm_usb_sram ((uint8_t *)0x40006000)
+
+struct stm_dma_channel {
+ vuint32_t ccr;
+ vuint32_t cndtr;
+ vvoid_t cpar;
+ vvoid_t cmar;
+ vuint32_t reserved;
+};
+
+#define STM_NUM_DMA 7
+
+struct stm_dma {
+ vuint32_t isr;
+ vuint32_t ifcr;
+ struct stm_dma_channel channel[STM_NUM_DMA];
+};
+
+extern struct stm_dma stm_dma;
+
+#define stm_dma (*((struct stm_dma *) 0x40020000))
+
+/* DMA channels go from 1 to 7, instead of 0 to 6 (sigh)
+ */
+
+#define STM_DMA_INDEX(channel) ((channel) - 1)
+
+#define STM_DMA_ISR(index) ((index) << 2)
+#define STM_DMA_ISR_MASK 0xfUL
+#define STM_DMA_ISR_TEIF 3
+#define STM_DMA_ISR_HTIF 2
+#define STM_DMA_ISR_TCIF 1
+#define STM_DMA_ISR_GIF 0
+
+#define STM_DMA_IFCR(index) ((index) << 2)
+#define STM_DMA_IFCR_MASK 0xfUL
+#define STM_DMA_IFCR_CTEIF 3
+#define STM_DMA_IFCR_CHTIF 2
+#define STM_DMA_IFCR_CTCIF 1
+#define STM_DMA_IFCR_CGIF 0
+
+#define STM_DMA_CCR_MEM2MEM (14)
+
+#define STM_DMA_CCR_PL (12)
+#define STM_DMA_CCR_PL_LOW (0)
+#define STM_DMA_CCR_PL_MEDIUM (1)
+#define STM_DMA_CCR_PL_HIGH (2)
+#define STM_DMA_CCR_PL_VERY_HIGH (3)
+#define STM_DMA_CCR_PL_MASK (3)
+
+#define STM_DMA_CCR_MSIZE (10)
+#define STM_DMA_CCR_MSIZE_8 (0)
+#define STM_DMA_CCR_MSIZE_16 (1)
+#define STM_DMA_CCR_MSIZE_32 (2)
+#define STM_DMA_CCR_MSIZE_MASK (3)
+
+#define STM_DMA_CCR_PSIZE (8)
+#define STM_DMA_CCR_PSIZE_8 (0)
+#define STM_DMA_CCR_PSIZE_16 (1)
+#define STM_DMA_CCR_PSIZE_32 (2)
+#define STM_DMA_CCR_PSIZE_MASK (3)
+
+#define STM_DMA_CCR_MINC (7)
+#define STM_DMA_CCR_PINC (6)
+#define STM_DMA_CCR_CIRC (5)
+#define STM_DMA_CCR_DIR (4)
+#define STM_DMA_CCR_DIR_PER_TO_MEM 0
+#define STM_DMA_CCR_DIR_MEM_TO_PER 1
+#define STM_DMA_CCR_TEIE (3)
+#define STM_DMA_CCR_HTIE (2)
+#define STM_DMA_CCR_TCIE (1)
+#define STM_DMA_CCR_EN (0)
+
+#define STM_DMA_CHANNEL_ADC1 1
+#define STM_DMA_CHANNEL_SPI1_RX 2
+#define STM_DMA_CHANNEL_SPI1_TX 3
+#define STM_DMA_CHANNEL_SPI2_RX 4
+#define STM_DMA_CHANNEL_SPI2_TX 5
+#define STM_DMA_CHANNEL_USART3_TX 2
+#define STM_DMA_CHANNEL_USART3_RX 3
+#define STM_DMA_CHANNEL_USART1_TX 4
+#define STM_DMA_CHANNEL_USART1_RX 5
+#define STM_DMA_CHANNEL_USART2_RX 6
+#define STM_DMA_CHANNEL_USART2_TX 7
+#define STM_DMA_CHANNEL_I2C2_TX 4
+#define STM_DMA_CHANNEL_I2C2_RX 5
+#define STM_DMA_CHANNEL_I2C1_TX 6
+#define STM_DMA_CHANNEL_I2C1_RX 7
+#define STM_DMA_CHANNEL_TIM1_CH1 2
+#define STM_DMA_CHANNEL_TIM1_CH4 4
+#define STM_DMA_CHANNEL_TIM1_TRIG 4
+#define STM_DMA_CHANNEL_TIM1_COM 4
+#define STM_DMA_CHANNEL_TIM1_UP 5
+#define STM_DMA_CHANNEL_TIM1_CH3 6
+#define STM_DMA_CHANNEL_TIM2_CH3 1
+#define STM_DMA_CHANNEL_TIM2_UP 2
+#define STM_DMA_CHANNEL_TIM2_CH1 5
+#define STM_DMA_CHANNEL_TIM2_CH2 7
+#define STM_DMA_CHANNEL_TIM2_CH4 7
+#define STM_DMA_CHANNEL_TIM3_CH3 2
+#define STM_DMA_CHANNEL_TIM3_CH4 3
+#define STM_DMA_CHANNEL_TIM3_UP 3
+#define STM_DMA_CHANNEL_TIM3_CH1 6
+#define STM_DMA_CHANNEL_TIM3_TRIG 6
+#define STM_DMA_CHANNEL_TIM4_CH1 1
+#define STM_DMA_CHANNEL_TIM4_CH2 4
+#define STM_DMA_CHANNEL_TIM4_CH3 5
+#define STM_DMA_CHANNEL_TIM4_UP 7
+
+/* high density, xl-density and connectivity devices also have dma2 */
+
+#define STM_DMA2_CHANNEL_ADC3 5
+#define STM_DMA2_CHANNEL_SPI3_RX 1
+#define STM_DMA2_CHANNEL_SPI3_TX 2
+#define STM_DMA2_CHANNEL_UART4_RX 3
+#define STM_DMA2_CHANNEL_UART4_TX 5
+#define STM_DMA2_CHANNEL_TIM5_CH4 1
+#define STM_DMA2_CHANNEL_TIM5_TRIG 1
+#define STM_DMA2_CHANNEL_TIM5_CH3 2
+#define STM_DMA2_CHANNEL_TIM5_UP 2
+#define STM_DMA2_CHANNEL_TIM5_CH2 4
+#define STM_DMA2_CHANNEL_TIM5_CH1 5
+#define STM_DMA2_CHANNEL_TIM6_UP 3
+#define STM_DMA2_CHANNEL_DAC_CHANNEL1 3
+#define STM_DMA2_CHANNEL_TIM7_UP 4
+#define STM_DMA2_CHANNEL_DAC_CHANNEL2 4
+#define STM_DMA2_CHANNEL_TIM8_CH3 1
+#define STM_DMA2_CHANNEL_TIM8_UP 1
+#define STM_DMA2_CHANNEL_TIM8_CH4 2
+#define STM_DMA2_CHANNEL_TIM8_TRIG 2
+#define STM_DMA2_CHANNEL_TIM8_COM 2
+#define STM_DMA2_CHANNEL_TIM8_CH1 3
+#define STM_DMA2_CHANNEL_TIM8_CH2 5
+
+struct stm_spi {
+ vuint32_t cr1;
+ vuint32_t cr2;
+ vuint32_t sr;
+ vuint32_t dr;
+
+ vuint32_t crcpr;
+ vuint32_t rxcrcr;
+ vuint32_t txcrcr;
+ vuint32_t i2scfgr;
+
+ vuint32_t i2spr;
+};
+
+extern struct stm_spi stm_spi1, stm_spi2;
+
+#define stm_spi1 (*((struct stm_spi *) 0x40013000))
+#define stm_spi2 (*((struct stm_spi *) 0x40003800))
+
+/* SPI channels go from 1 to 2, instead of 0 to 1 (sigh)
+ */
+
+#define STM_NUM_SPI 2
+
+#define STM_SPI_INDEX(channel) ((channel) - 1)
+
+#define STM_SPI_CR1_BIDIMODE 15
+#define STM_SPI_CR1_BIDIOE 14
+#define STM_SPI_CR1_CRCEN 13
+#define STM_SPI_CR1_CRCNEXT 12
+#define STM_SPI_CR1_DFF 11
+#define STM_SPI_CR1_RXONLY 10
+#define STM_SPI_CR1_SSM 9
+#define STM_SPI_CR1_SSI 8
+#define STM_SPI_CR1_LSBFIRST 7
+#define STM_SPI_CR1_SPE 6
+#define STM_SPI_CR1_BR 3
+#define STM_SPI_CR1_BR_PCLK_2 0
+#define STM_SPI_CR1_BR_PCLK_4 1
+#define STM_SPI_CR1_BR_PCLK_8 2
+#define STM_SPI_CR1_BR_PCLK_16 3
+#define STM_SPI_CR1_BR_PCLK_32 4
+#define STM_SPI_CR1_BR_PCLK_64 5
+#define STM_SPI_CR1_BR_PCLK_128 6
+#define STM_SPI_CR1_BR_PCLK_256 7
+#define STM_SPI_CR1_BR_MASK 7UL
+
+#define STM_SPI_CR1_MSTR 2
+#define STM_SPI_CR1_CPOL 1
+#define STM_SPI_CR1_CPHA 0
+
+#define STM_SPI_CR2_TXEIE 7
+#define STM_SPI_CR2_RXNEIE 6
+#define STM_SPI_CR2_ERRIE 5
+#define STM_SPI_CR2_SSOE 2
+#define STM_SPI_CR2_TXDMAEN 1
+#define STM_SPI_CR2_RXDMAEN 0
+
+#define STM_SPI_SR_FRE 8
+#define STM_SPI_SR_BSY 7
+#define STM_SPI_SR_OVR 6
+#define STM_SPI_SR_MODF 5
+#define STM_SPI_SR_CRCERR 4
+#define STM_SPI_SR_UDR 3
+#define STM_SPI_SR_CHSIDE 2
+#define STM_SPI_SR_TXE 1
+#define STM_SPI_SR_RXNE 0
+
+#define STM_NUM_I2C 2
+
+#define STM_I2C_INDEX(channel) ((channel) - 1)
+
+struct stm_i2c {
+ vuint32_t cr1;
+ vuint32_t cr2;
+ vuint32_t oar1;
+ vuint32_t oar2;
+ vuint32_t dr;
+ vuint32_t sr1;
+ vuint32_t sr2;
+ vuint32_t ccr;
+ vuint32_t trise;
+};
+
+extern struct stm_i2c stm_i2c1, stm_i2c2;
+
+#define stm_i2c1 (*((struct stm_i2c *) 0x40005400))
+#define stm_i2c2 (*((struct stm_i2c *) 0x40005800))
+
+#define STM_I2C_CR1_SWRST 15
+#define STM_I2C_CR1_ALERT 13
+#define STM_I2C_CR1_PEC 12
+#define STM_I2C_CR1_POS 11
+#define STM_I2C_CR1_ACK 10
+#define STM_I2C_CR1_STOP 9
+#define STM_I2C_CR1_START 8
+#define STM_I2C_CR1_NOSTRETCH 7
+#define STM_I2C_CR1_ENGC 6
+#define STM_I2C_CR1_ENPEC 5
+#define STM_I2C_CR1_ENARP 4
+#define STM_I2C_CR1_SMBTYPE 3
+#define STM_I2C_CR1_SMBUS 1
+#define STM_I2C_CR1_PE 0
+
+#define STM_I2C_CR2_LAST 12
+#define STM_I2C_CR2_DMAEN 11
+#define STM_I2C_CR2_ITBUFEN 10
+#define STM_I2C_CR2_ITEVTEN 9
+#define STM_I2C_CR2_ITERREN 8
+#define STM_I2C_CR2_FREQ 0
+#define STM_I2C_CR2_FREQ_MASK 0x3fUL
+
+#define STM_I2C_SR1_SMBALERT 15
+#define STM_I2C_SR1_TIMEOUT 14
+#define STM_I2C_SR1_PECERR 12
+#define STM_I2C_SR1_OVR 11
+#define STM_I2C_SR1_AF 10
+#define STM_I2C_SR1_ARLO 9
+#define STM_I2C_SR1_BERR 8
+#define STM_I2C_SR1_TXE 7
+#define STM_I2C_SR1_RXNE 6
+#define STM_I2C_SR1_STOPF 4
+#define STM_I2C_SR1_ADD10 3
+#define STM_I2C_SR1_BTF 2
+#define STM_I2C_SR1_ADDR 1
+#define STM_I2C_SR1_SB 0
+
+#define STM_I2C_SR2_PEC 8
+#define STM_I2C_SR2_PEC_MASK 0xff00UL
+#define STM_I2C_SR2_DUALF 7
+#define STM_I2C_SR2_SMBHOST 6
+#define STM_I2C_SR2_SMBDEFAULT 5
+#define STM_I2C_SR2_GENCALL 4
+#define STM_I2C_SR2_TRA 2
+#define STM_I2C_SR2_BUSY 1
+#define STM_I2C_SR2_MSL 0
+
+#define STM_I2C_CCR_FS 15
+#define STM_I2C_CCR_DUTY 14
+#define STM_I2C_CCR_CCR 0
+#define STM_I2C_CCR_MASK 0x7ffUL
+
+struct stm_adc {
+ vuint32_t sr;
+ vuint32_t cr1;
+ vuint32_t cr2;
+ vuint32_t smpr1;
+
+ vuint32_t smpr2;
+ vuint32_t jofr1;
+ vuint32_t jofr2;
+ vuint32_t jofr3;
+
+ vuint32_t jofr4;
+ vuint32_t htr;
+ vuint32_t ltr;
+ vuint32_t sqr1;
+
+ vuint32_t sqr2;
+ vuint32_t sqr3;
+ vuint32_t jsqr;
+ vuint32_t jdr1;
+
+ vuint32_t jdr2;
+ vuint32_t jdr3;
+ vuint32_t jdr4;
+ vuint32_t dr;
+};
+
+extern struct stm_adc stm_adc1;
+
+//#define stm_adc1 (*((struct stm_adc *) 0x40012400))
+
+#define STM_ADC_SQ_TEMP 16
+#define STM_ADC_SQ_V_REF 17
+
+#define STM_ADC_SR_STRT 4
+#define STM_ADC_SR_JSTRT 3
+#define STM_ADC_SR_JEOC 2
+#define STM_ADC_SR_EOC 1
+#define STM_ADC_SR_AWD 0
+
+#define STM_ADC_CR1_AWDEN 23
+#define STM_ADC_CR1_JAWDEN 22
+#define STM_ADC_CR1_DUALMOD 16
+# define STM_ADC_CR1_DUALMOD_INDEPENDENT 0
+# define STM_ADC_CR1_DUALMOD_COMB_REG_SIM_INJ_SIM 1
+# define STM_ADC_CR1_DUALMOD_COMB_REG_SIM_ALT_TRIG 2
+# define STM_ADC_CR1_DUALMOD_COMB_INJ_SIM_FAST_INT 3
+# define STM_ADC_CR1_DUALMOD_COMB_INJ_SIM_SLOW_INT 4
+# define STM_ADC_CR1_DUALMOD_INJ_SIM 5
+# define STM_ADC_CR1_DUALMOD_REG_SIM 6
+# define STM_ADC_CR1_DUALMOD_FAST_INT 7
+# define STM_ADC_CR1_DUALMOD_SLOW_INT 8
+# define STM_ADC_CR1_DUALMOD_ALT_TRIG 9
+
+#define STM_ADC_CR1_DISCNUM 13
+#define STM_ADC_CR1_DISCNUM_1 0
+#define STM_ADC_CR1_DISCNUM_2 1
+#define STM_ADC_CR1_DISCNUM_3 2
+#define STM_ADC_CR1_DISCNUM_4 3
+#define STM_ADC_CR1_DISCNUM_5 4
+#define STM_ADC_CR1_DISCNUM_6 5
+#define STM_ADC_CR1_DISCNUM_7 6
+#define STM_ADC_CR1_DISCNUM_8 7
+#define STM_ADC_CR1_DISCNUM_MASK 7UL
+#define STM_ADC_CR1_JDISCEN 12
+#define STM_ADC_CR1_DISCEN 11
+#define STM_ADC_CR1_JAUTO 10
+#define STM_ADC_CR1_AWDSGL 9
+#define STM_ADC_CR1_SCAN 8
+#define STM_ADC_CR1_JEOCIE 7
+#define STM_ADC_CR1_AWDIE 6
+#define STM_ADC_CR1_EOCIE 5
+#define STM_ADC_CR1_AWDCH 0
+#define STM_ADC_CR1_AWDCH_MASK 0x1fUL
+
+#define STM_ADC_CR2_TSVREF 23
+#define STM_ADC_CR2_SWSTART 22
+#define STM_ADC_CR2_JWSTART 21
+#define STM_ADC_CR2_EXTTRIG 20
+#define STM_ADC_CR2_EXTSEL 17
+#define STM_ADC_CR2_EXTSEL_TIM1_CC1 0
+#define STM_ADC_CR2_EXTSEL_TIM1_CC2 1
+#define STM_ADC_CR2_EXTSEL_TIM1_CC3 2
+#define STM_ADC_CR2_EXTSEL_TIM2_CC2 3
+#define STM_ADC_CR2_EXTSEL_TIM3_TRGO 4
+#define STM_ADC_CR2_EXTSEL_TIM4_CC4 5
+#define STM_ADC_CR2_EXTSEL_EXTI 6
+#define STM_ADC_CR2_EXTSEL_SWSTART 7
+#define STM_ADC_CR2_EXTSEL_MASK 7UL
+#define STM_ADC_CR2_JEXTTRIG 15
+#define STM_ADC_CR2_JEXTSEL 12
+#define STM_ADC_CR2_JEXTSEL_TIM1_TRGO 0
+#define STM_ADC_CR2_JEXTSEL_TIM1_CC4 1
+#define STM_ADC_CR2_JEXTSEL_TIM2_TRGO 2
+#define STM_ADC_CR2_JEXTSEL_TIM2_CC1 3
+#define STM_ADC_CR2_JEXTSEL_TIM3_CC4 4
+#define STM_ADC_CR2_JEXTSEL_TIM4_TRGO 5
+#define STM_ADC_CR2_JEXTSEL_EXTI_15 6
+#define STM_ADC_CR2_JEXTSEL_JSWSTART 7
+#define STM_ADC_CR2_JEXTSEL_MASK 7UL
+#define STM_ADC_CR2_ALIGN 11
+#define STM_ADC_CR2_DMA 8
+#define STM_ADC_CR2_RSTCAL 3
+#define STM_ADC_CR2_CAL 2
+#define STM_ADC_CR2_CONT 1
+#define STM_ADC_CR2_ADON 0
+
+struct stm_exti {
+ vuint32_t imr;
+ vuint32_t emr;
+ vuint32_t rtsr;
+ vuint32_t ftsr;
+
+ vuint32_t swier;
+ vuint32_t pr;
+};
+
+extern struct stm_exti stm_exti;
+
+#define stm_exti (*((struct stm_exti *) 0x40010400))
+
+static inline void
+stm_exticr_set(struct stm_gpio *gpio, int pin) {
+ uint8_t reg = (uint8_t) (pin >> 2);
+ uint8_t shift = (pin & 3) << 2;
+ uint8_t val = 0;
+
+ if (gpio == &stm_gpioa)
+ val = STM_AFIO_EXTICR_PA;
+ else if (gpio == &stm_gpiob)
+ val = STM_AFIO_EXTICR_PB;
+ else if (gpio == &stm_gpioc)
+ val = STM_AFIO_EXTICR_PC;
+ else if (gpio == &stm_gpiod)
+ val = STM_AFIO_EXTICR_PD;
+ else if (gpio == &stm_gpioe)
+ val = STM_AFIO_EXTICR_PE;
+
+ stm_afio.exticr[reg] = (stm_afio.exticr[reg] & (uint32_t) ~(0xf << shift)) | val << shift;
+}
+
+struct stm_tim18 {
+ vuint32_t cr1;
+ vuint32_t cr2;
+ vuint32_t smcr;
+ vuint32_t dier;
+
+ vuint32_t sr;
+ vuint32_t egr;
+ vuint32_t ccmr1;
+ vuint32_t ccmr2;
+
+ vuint32_t ccer;
+ vuint32_t cnt;
+ vuint32_t psc;
+ vuint32_t arr;
+
+ vuint32_t rcr;
+ vuint32_t ccr1;
+ vuint32_t ccr2;
+ vuint32_t ccr3;
+
+ vuint32_t ccr4;
+ uint32_t bdtr;
+ vuint32_t dcr;
+ vuint32_t dmar;
+};
+
+extern struct stm_tim18 stm_tim1, stm_tim8;
+
+#define stm_tim1 (*((struct stm_tim18 *) 0x40012c00))
+#define stm_tim8 (*((struct stm_tim18 *) 0x40013400))
+
+#define STM_TIM18_CR1_CKD 8
+#define STM_TIM18_CR1_CKD_1 0
+#define STM_TIM18_CR1_CKD_2 1
+#define STM_TIM18_CR1_CKD_4 2
+#define STM_TIM18_CR1_CKD_MASK 3UL
+#define STM_TIM18_CR1_ARPE 7
+#define STM_TIM18_CR1_CMS 5
+#define STM_TIM18_CR1_CMS_EDGE 0
+#define STM_TIM18_CR1_CMS_CENTER_1 1
+#define STM_TIM18_CR1_CMS_CENTER_2 2
+#define STM_TIM18_CR1_CMS_CENTER_3 3
+#define STM_TIM18_CR1_CMS_MASK 3UL
+#define STM_TIM18_CR1_DIR 4
+#define STM_TIM18_CR1_DIR_UP 0
+#define STM_TIM18_CR1_DIR_DOWN 1
+#define STM_TIM18_CR1_OPM 3
+#define STM_TIM18_CR1_URS 2
+#define STM_TIM18_CR1_UDIS 1
+#define STM_TIM18_CR1_CEN 0
+
+#define STM_TIM18_CR2_TI1S 7
+#define STM_TIM18_CR2_MMS 4
+#define STM_TIM18_CR2_MMS_RESET 0
+#define STM_TIM18_CR2_MMS_ENABLE 1
+#define STM_TIM18_CR2_MMS_UPDATE 2
+#define STM_TIM18_CR2_MMS_COMPARE_PULSE 3
+#define STM_TIM18_CR2_MMS_COMPARE_OC1REF 4
+#define STM_TIM18_CR2_MMS_COMPARE_OC2REF 5
+#define STM_TIM18_CR2_MMS_COMPARE_OC3REF 6
+#define STM_TIM18_CR2_MMS_COMPARE_OC4REF 7
+#define STM_TIM18_CR2_MMS_MASK 7UL
+#define STM_TIM18_CR2_CCDS 3
+
+#define STM_TIM18_SMCR_ETP 15
+#define STM_TIM18_SMCR_ECE 14
+#define STM_TIM18_SMCR_ETPS 12
+#define STM_TIM18_SMCR_ETPS_OFF 0
+#define STM_TIM18_SMCR_ETPS_DIV_2 1
+#define STM_TIM18_SMCR_ETPS_DIV_4 2
+#define STM_TIM18_SMCR_ETPS_DIV_8 3
+#define STM_TIM18_SMCR_ETPS_MASK 3UL
+#define STM_TIM18_SMCR_ETF 8
+#define STM_TIM18_SMCR_ETF_NONE 0
+#define STM_TIM18_SMCR_ETF_INT_N_2 1
+#define STM_TIM18_SMCR_ETF_INT_N_4 2
+#define STM_TIM18_SMCR_ETF_INT_N_8 3
+#define STM_TIM18_SMCR_ETF_DTS_2_N_6 4
+#define STM_TIM18_SMCR_ETF_DTS_2_N_8 5
+#define STM_TIM18_SMCR_ETF_DTS_4_N_6 6
+#define STM_TIM18_SMCR_ETF_DTS_4_N_8 7
+#define STM_TIM18_SMCR_ETF_DTS_8_N_6 8
+#define STM_TIM18_SMCR_ETF_DTS_8_N_8 9
+#define STM_TIM18_SMCR_ETF_DTS_16_N_5 10
+#define STM_TIM18_SMCR_ETF_DTS_16_N_6 11
+#define STM_TIM18_SMCR_ETF_DTS_16_N_8 12
+#define STM_TIM18_SMCR_ETF_DTS_32_N_5 13
+#define STM_TIM18_SMCR_ETF_DTS_32_N_6 14
+#define STM_TIM18_SMCR_ETF_DTS_32_N_8 15
+#define STM_TIM18_SMCR_ETF_MASK 15UL
+#define STM_TIM18_SMCR_MSM 7
+#define STM_TIM18_SMCR_TS 4
+#define STM_TIM18_SMCR_TS_ITR0 0
+#define STM_TIM18_SMCR_TS_ITR1 1
+#define STM_TIM18_SMCR_TS_ITR2 2
+#define STM_TIM18_SMCR_TS_ITR3 3
+#define STM_TIM18_SMCR_TS_TI1F_ED 4
+#define STM_TIM18_SMCR_TS_TI1FP1 5
+#define STM_TIM18_SMCR_TS_TI2FP2 6
+#define STM_TIM18_SMCR_TS_ETRF 7
+#define STM_TIM18_SMCR_TS_MASK 7UL
+#define STM_TIM18_SMCR_SMS 0
+#define STM_TIM18_SMCR_SMS_DISABLE 0
+#define STM_TIM18_SMCR_SMS_ENCODER_MODE_1 1
+#define STM_TIM18_SMCR_SMS_ENCODER_MODE_2 2
+#define STM_TIM18_SMCR_SMS_ENCODER_MODE_3 3
+#define STM_TIM18_SMCR_SMS_RESET_MODE 4
+#define STM_TIM18_SMCR_SMS_GATED_MODE 5
+#define STM_TIM18_SMCR_SMS_TRIGGER_MODE 6
+#define STM_TIM18_SMCR_SMS_EXTERNAL_CLOCK 7
+#define STM_TIM18_SMCR_SMS_MASK 7UL
+
+#define STM_TIM18_DIER_TDE 14
+#define STM_TIM18_DIER_CC4DE 12
+#define STM_TIM18_DIER_CC3DE 11
+#define STM_TIM18_DIER_CC2DE 10
+#define STM_TIM18_DIER_CC1DE 9
+#define STM_TIM18_DIER_UDE 8
+
+#define STM_TIM18_DIER_TIE 6
+#define STM_TIM18_DIER_CC4IE 4
+#define STM_TIM18_DIER_CC3IE 3
+#define STM_TIM18_DIER_CC2IE 2
+#define STM_TIM18_DIER_CC1IE 1
+#define STM_TIM18_DIER_UIE 0
+
+#define STM_TIM18_SR_CC4OF 12
+#define STM_TIM18_SR_CC3OF 11
+#define STM_TIM18_SR_CC2OF 10
+#define STM_TIM18_SR_CC1OF 9
+#define STM_TIM18_SR_TIF 6
+#define STM_TIM18_SR_CC4IF 4
+#define STM_TIM18_SR_CC3IF 3
+#define STM_TIM18_SR_CC2IF 2
+#define STM_TIM18_SR_CC1IF 1
+#define STM_TIM18_SR_UIF 0
+
+#define STM_TIM18_EGR_TG 6
+#define STM_TIM18_EGR_CC4G 4
+#define STM_TIM18_EGR_CC3G 3
+#define STM_TIM18_EGR_CC2G 2
+#define STM_TIM18_EGR_CC1G 1
+#define STM_TIM18_EGR_UG 0
+
+#define STM_TIM18_CCMR1_OC2CE 15
+#define STM_TIM18_CCMR1_OC2M 12
+#define STM_TIM18_CCMR1_OC2M_FROZEN 0
+#define STM_TIM18_CCMR1_OC2M_SET_HIGH_ON_MATCH 1
+#define STM_TIM18_CCMR1_OC2M_SET_LOW_ON_MATCH 2
+#define STM_TIM18_CCMR1_OC2M_TOGGLE 3
+#define STM_TIM18_CCMR1_OC2M_FORCE_LOW 4
+#define STM_TIM18_CCMR1_OC2M_FORCE_HIGH 5
+#define STM_TIM18_CCMR1_OC2M_PWM_MODE_1 6
+#define STM_TIM18_CCMR1_OC2M_PWM_MODE_2 7
+#define STM_TIM18_CCMR1_OC2M_MASK 7UL
+#define STM_TIM18_CCMR1_OC2PE 11
+#define STM_TIM18_CCMR1_OC2FE 10
+#define STM_TIM18_CCMR1_CC2S 8
+#define STM_TIM18_CCMR1_CC2S_OUTPUT 0
+#define STM_TIM18_CCMR1_CC2S_INPUT_TI2 1
+#define STM_TIM18_CCMR1_CC2S_INPUT_TI1 2
+#define STM_TIM18_CCMR1_CC2S_INPUT_TRC 3
+#define STM_TIM18_CCMR1_CC2S_MASK 3UL
+
+#define STM_TIM18_CCMR1_OC1CE 7
+#define STM_TIM18_CCMR1_OC1M 4
+#define STM_TIM18_CCMR1_OC1M_FROZEN 0
+#define STM_TIM18_CCMR1_OC1M_SET_HIGH_ON_MATCH 1
+#define STM_TIM18_CCMR1_OC1M_SET_LOW_ON_MATCH 2
+#define STM_TIM18_CCMR1_OC1M_TOGGLE 3
+#define STM_TIM18_CCMR1_OC1M_FORCE_LOW 4
+#define STM_TIM18_CCMR1_OC1M_FORCE_HIGH 5
+#define STM_TIM18_CCMR1_OC1M_PWM_MODE_1 6
+#define STM_TIM18_CCMR1_OC1M_PWM_MODE_2 7
+#define STM_TIM18_CCMR1_OC1M_MASK 7UL
+#define STM_TIM18_CCMR1_OC1PE 3
+#define STM_TIM18_CCMR1_OC1FE 2
+#define STM_TIM18_CCMR1_CC1S 0
+#define STM_TIM18_CCMR1_CC1S_OUTPUT 0
+#define STM_TIM18_CCMR1_CC1S_INPUT_TI1 1
+#define STM_TIM18_CCMR1_CC1S_INPUT_TI2 2
+#define STM_TIM18_CCMR1_CC1S_INPUT_TRC 3
+#define STM_TIM18_CCMR1_CC1S_MASK 3UL
+
+#define STM_TIM18_CCMR1_IC2F 12
+#define STM_TIM18_CCMR1_IC2F_NONE 0
+#define STM_TIM18_CCMR1_IC2F_CK_INT_N_2 1
+#define STM_TIM18_CCMR1_IC2F_CK_INT_N_4 2
+#define STM_TIM18_CCMR1_IC2F_CK_INT_N_8 3
+#define STM_TIM18_CCMR1_IC2F_DTS_2_N_6 4
+#define STM_TIM18_CCMR1_IC2F_DTS_2_N_8 5
+#define STM_TIM18_CCMR1_IC2F_DTS_4_N_6 6
+#define STM_TIM18_CCMR1_IC2F_DTS_4_N_8 7
+#define STM_TIM18_CCMR1_IC2F_DTS_8_N_6 8
+#define STM_TIM18_CCMR1_IC2F_DTS_8_N_8 9
+#define STM_TIM18_CCMR1_IC2F_DTS_16_N_5 10
+#define STM_TIM18_CCMR1_IC2F_DTS_16_N_6 11
+#define STM_TIM18_CCMR1_IC2F_DTS_16_N_8 12
+#define STM_TIM18_CCMR1_IC2F_DTS_32_N_5 13
+#define STM_TIM18_CCMR1_IC2F_DTS_32_N_6 14
+#define STM_TIM18_CCMR1_IC2F_DTS_32_N_8 15
+#define STM_TIM18_CCMR1_IC2PSC 10
+#define STM_TIM18_CCMR1_IC2PSC_NONE 0
+#define STM_TIM18_CCMR1_IC2PSC_2 1
+#define STM_TIM18_CCMR1_IC2PSC_4 2
+#define STM_TIM18_CCMR1_IC2PSC_8 3
+#define STM_TIM18_CCMR1_IC1F 4
+#define STM_TIM18_CCMR1_IC1F_NONE 0
+#define STM_TIM18_CCMR1_IC1F_CK_INT_N_2 1
+#define STM_TIM18_CCMR1_IC1F_CK_INT_N_4 2
+#define STM_TIM18_CCMR1_IC1F_CK_INT_N_8 3
+#define STM_TIM18_CCMR1_IC1F_DTS_2_N_6 4
+#define STM_TIM18_CCMR1_IC1F_DTS_2_N_8 5
+#define STM_TIM18_CCMR1_IC1F_DTS_4_N_6 6
+#define STM_TIM18_CCMR1_IC1F_DTS_4_N_8 7
+#define STM_TIM18_CCMR1_IC1F_DTS_8_N_6 8
+#define STM_TIM18_CCMR1_IC1F_DTS_8_N_8 9
+#define STM_TIM18_CCMR1_IC1F_DTS_16_N_5 10
+#define STM_TIM18_CCMR1_IC1F_DTS_16_N_6 11
+#define STM_TIM18_CCMR1_IC1F_DTS_16_N_8 12
+#define STM_TIM18_CCMR1_IC1F_DTS_32_N_5 13
+#define STM_TIM18_CCMR1_IC1F_DTS_32_N_6 14
+#define STM_TIM18_CCMR1_IC1F_DTS_32_N_8 15
+#define STM_TIM18_CCMR1_IC1PSC 2
+#define STM_TIM18_CCMR1_IC1PSC_NONE 0
+#define STM_TIM18_CCMR1_IC1PSC_2 1
+#define STM_TIM18_CCMR1_IC1PSC_4 2
+#define STM_TIM18_CCMR1_IC1PSC_8 3
+
+#define STM_TIM18_CCMR2_OC4CE 15
+#define STM_TIM18_CCMR2_OC4M 12
+#define STM_TIM18_CCMR2_OC4M_FROZEN 0
+#define STM_TIM18_CCMR2_OC4M_SET_HIGH_ON_MATCH 1
+#define STM_TIM18_CCMR2_OC4M_SET_LOW_ON_MATCH 2
+#define STM_TIM18_CCMR2_OC4M_TOGGLE 3
+#define STM_TIM18_CCMR2_OC4M_FORCE_LOW 4
+#define STM_TIM18_CCMR2_OC4M_FORCE_HIGH 5
+#define STM_TIM18_CCMR2_OC4M_PWM_MODE_1 6
+#define STM_TIM18_CCMR2_OC4M_PWM_MODE_2 7
+#define STM_TIM18_CCMR2_OC4M_MASK 7UL
+#define STM_TIM18_CCMR2_OC4PE 11
+#define STM_TIM18_CCMR2_OC4FE 10
+#define STM_TIM18_CCMR2_CC4S 8
+#define STM_TIM18_CCMR2_CC4S_OUTPUT 0
+#define STM_TIM18_CCMR2_CC4S_INPUT_TI4 1
+#define STM_TIM18_CCMR2_CC4S_INPUT_TI3 2
+#define STM_TIM18_CCMR2_CC4S_INPUT_TRC 3
+#define STM_TIM18_CCMR2_CC4S_MASK 3UL
+
+#define STM_TIM18_CCMR2_OC3CE 7
+#define STM_TIM18_CCMR2_OC3M 4
+#define STM_TIM18_CCMR2_OC3M_FROZEN 0
+#define STM_TIM18_CCMR2_OC3M_SET_HIGH_ON_MATCH 1
+#define STM_TIM18_CCMR2_OC3M_SET_LOW_ON_MATCH 2
+#define STM_TIM18_CCMR2_OC3M_TOGGLE 3
+#define STM_TIM18_CCMR2_OC3M_FORCE_LOW 4
+#define STM_TIM18_CCMR2_OC3M_FORCE_HIGH 5
+#define STM_TIM18_CCMR2_OC3M_PWM_MODE_1 6
+#define STM_TIM18_CCMR2_OC3M_PWM_MODE_2 7
+#define STM_TIM18_CCMR2_OC3M_MASK 7UL
+#define STM_TIM18_CCMR2_OC3PE 3
+#define STM_TIM18_CCMR2_OC3FE 2
+#define STM_TIM18_CCMR2_CC3S 0
+#define STM_TIM18_CCMR2_CC3S_OUTPUT 0
+#define STM_TIM18_CCMR2_CC3S_INPUT_TI3 1
+#define STM_TIM18_CCMR2_CC3S_INPUT_TI4 2
+#define STM_TIM18_CCMR2_CC3S_INPUT_TRC 3
+#define STM_TIM18_CCMR2_CC3S_MASK 3UL
+
+#define STM_TIM18_CCER_CC4NP 15
+#define STM_TIM18_CCER_CC4P 13
+#define STM_TIM18_CCER_CC4P_ACTIVE_HIGH 0
+#define STM_TIM18_CCER_CC4P_ACTIVE_LOW 1
+#define STM_TIM18_CCER_CC4E 12
+#define STM_TIM18_CCER_CC3NP 11
+#define STM_TIM18_CCER_CC3P 9
+#define STM_TIM18_CCER_CC3P_ACTIVE_HIGH 0
+#define STM_TIM18_CCER_CC3P_ACTIVE_LOW 1
+#define STM_TIM18_CCER_CC3E 8
+#define STM_TIM18_CCER_CC2NP 7
+#define STM_TIM18_CCER_CC2P 5
+#define STM_TIM18_CCER_CC2P_ACTIVE_HIGH 0
+#define STM_TIM18_CCER_CC2P_ACTIVE_LOW 1
+#define STM_TIM18_CCER_CC2E 4
+#define STM_TIM18_CCER_CC1NP 3
+#define STM_TIM18_CCER_CC1P 1
+#define STM_TIM18_CCER_CC1P_ACTIVE_HIGH 0
+#define STM_TIM18_CCER_CC1P_ACTIVE_LOW 1
+#define STM_TIM18_CCER_CC1E 0
+
+struct stm_tim234 {
+ vuint32_t cr1;
+ vuint32_t cr2;
+ vuint32_t smcr;
+ vuint32_t dier;
+
+ vuint32_t sr;
+ vuint32_t egr;
+ vuint32_t ccmr1;
+ vuint32_t ccmr2;
+
+ vuint32_t ccer;
+ vuint32_t cnt;
+ vuint32_t psc;
+ vuint32_t arr;
+
+ uint32_t reserved_30;
+ vuint32_t ccr1;
+ vuint32_t ccr2;
+ vuint32_t ccr3;
+
+ vuint32_t ccr4;
+ uint32_t reserved_44;
+ vuint32_t dcr;
+ vuint32_t dmar;
+};
+
+extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
+
+#define stm_tim2 (*((struct stm_tim234 *) 0x40000000))
+#define stm_tim3 (*((struct stm_tim234 *) 0x40000400))
+#define stm_tim4 (*((struct stm_tim234 *) 0x40000800))
+
+#define STM_TIM234_CR1_CKD 8
+#define STM_TIM234_CR1_CKD_1 0
+#define STM_TIM234_CR1_CKD_2 1
+#define STM_TIM234_CR1_CKD_4 2
+#define STM_TIM234_CR1_CKD_MASK 3UL
+#define STM_TIM234_CR1_ARPE 7
+#define STM_TIM234_CR1_CMS 5
+#define STM_TIM234_CR1_CMS_EDGE 0
+#define STM_TIM234_CR1_CMS_CENTER_1 1
+#define STM_TIM234_CR1_CMS_CENTER_2 2
+#define STM_TIM234_CR1_CMS_CENTER_3 3
+#define STM_TIM234_CR1_CMS_MASK 3UL
+#define STM_TIM234_CR1_DIR 4
+#define STM_TIM234_CR1_DIR_UP 0
+#define STM_TIM234_CR1_DIR_DOWN 1
+#define STM_TIM234_CR1_OPM 3
+#define STM_TIM234_CR1_URS 2
+#define STM_TIM234_CR1_UDIS 1
+#define STM_TIM234_CR1_CEN 0
+
+#define STM_TIM234_CR2_TI1S 7
+#define STM_TIM234_CR2_MMS 4
+#define STM_TIM234_CR2_MMS_RESET 0
+#define STM_TIM234_CR2_MMS_ENABLE 1
+#define STM_TIM234_CR2_MMS_UPDATE 2
+#define STM_TIM234_CR2_MMS_COMPARE_PULSE 3
+#define STM_TIM234_CR2_MMS_COMPARE_OC1REF 4
+#define STM_TIM234_CR2_MMS_COMPARE_OC2REF 5
+#define STM_TIM234_CR2_MMS_COMPARE_OC3REF 6
+#define STM_TIM234_CR2_MMS_COMPARE_OC4REF 7
+#define STM_TIM234_CR2_MMS_MASK 7UL
+#define STM_TIM234_CR2_CCDS 3
+
+#define STM_TIM234_SMCR_ETP 15
+#define STM_TIM234_SMCR_ECE 14
+#define STM_TIM234_SMCR_ETPS 12
+#define STM_TIM234_SMCR_ETPS_OFF 0
+#define STM_TIM234_SMCR_ETPS_DIV_2 1
+#define STM_TIM234_SMCR_ETPS_DIV_4 2
+#define STM_TIM234_SMCR_ETPS_DIV_8 3
+#define STM_TIM234_SMCR_ETPS_MASK 3UL
+#define STM_TIM234_SMCR_ETF 8
+#define STM_TIM234_SMCR_ETF_NONE 0
+#define STM_TIM234_SMCR_ETF_INT_N_2 1
+#define STM_TIM234_SMCR_ETF_INT_N_4 2
+#define STM_TIM234_SMCR_ETF_INT_N_8 3
+#define STM_TIM234_SMCR_ETF_DTS_2_N_6 4
+#define STM_TIM234_SMCR_ETF_DTS_2_N_8 5
+#define STM_TIM234_SMCR_ETF_DTS_4_N_6 6
+#define STM_TIM234_SMCR_ETF_DTS_4_N_8 7
+#define STM_TIM234_SMCR_ETF_DTS_8_N_6 8
+#define STM_TIM234_SMCR_ETF_DTS_8_N_8 9
+#define STM_TIM234_SMCR_ETF_DTS_16_N_5 10
+#define STM_TIM234_SMCR_ETF_DTS_16_N_6 11
+#define STM_TIM234_SMCR_ETF_DTS_16_N_8 12
+#define STM_TIM234_SMCR_ETF_DTS_32_N_5 13
+#define STM_TIM234_SMCR_ETF_DTS_32_N_6 14
+#define STM_TIM234_SMCR_ETF_DTS_32_N_8 15
+#define STM_TIM234_SMCR_ETF_MASK 15UL
+#define STM_TIM234_SMCR_MSM 7
+#define STM_TIM234_SMCR_TS 4
+#define STM_TIM234_SMCR_TS_ITR0 0
+#define STM_TIM234_SMCR_TS_ITR1 1
+#define STM_TIM234_SMCR_TS_ITR2 2
+#define STM_TIM234_SMCR_TS_ITR3 3
+#define STM_TIM234_SMCR_TS_TI1F_ED 4
+#define STM_TIM234_SMCR_TS_TI1FP1 5
+#define STM_TIM234_SMCR_TS_TI2FP2 6
+#define STM_TIM234_SMCR_TS_ETRF 7
+#define STM_TIM234_SMCR_TS_MASK 7UL
+#define STM_TIM234_SMCR_SMS 0
+#define STM_TIM234_SMCR_SMS_DISABLE 0
+#define STM_TIM234_SMCR_SMS_ENCODER_MODE_1 1
+#define STM_TIM234_SMCR_SMS_ENCODER_MODE_2 2
+#define STM_TIM234_SMCR_SMS_ENCODER_MODE_3 3
+#define STM_TIM234_SMCR_SMS_RESET_MODE 4
+#define STM_TIM234_SMCR_SMS_GATED_MODE 5
+#define STM_TIM234_SMCR_SMS_TRIGGER_MODE 6
+#define STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK 7
+#define STM_TIM234_SMCR_SMS_MASK 7UL
+
+#define STM_TIM234_DIER_TDE 14
+#define STM_TIM234_DIER_CC4DE 12
+#define STM_TIM234_DIER_CC3DE 11
+#define STM_TIM234_DIER_CC2DE 10
+#define STM_TIM234_DIER_CC1DE 9
+#define STM_TIM234_DIER_UDE 8
+
+#define STM_TIM234_DIER_TIE 6
+#define STM_TIM234_DIER_CC4IE 4
+#define STM_TIM234_DIER_CC3IE 3
+#define STM_TIM234_DIER_CC2IE 2
+#define STM_TIM234_DIER_CC1IE 1
+#define STM_TIM234_DIER_UIE 0
+
+#define STM_TIM234_SR_CC4OF 12
+#define STM_TIM234_SR_CC3OF 11
+#define STM_TIM234_SR_CC2OF 10
+#define STM_TIM234_SR_CC1OF 9
+#define STM_TIM234_SR_TIF 6
+#define STM_TIM234_SR_CC4IF 4
+#define STM_TIM234_SR_CC3IF 3
+#define STM_TIM234_SR_CC2IF 2
+#define STM_TIM234_SR_CC1IF 1
+#define STM_TIM234_SR_UIF 0
+
+#define STM_TIM234_EGR_TG 6
+#define STM_TIM234_EGR_CC4G 4
+#define STM_TIM234_EGR_CC3G 3
+#define STM_TIM234_EGR_CC2G 2
+#define STM_TIM234_EGR_CC1G 1
+#define STM_TIM234_EGR_UG 0
+
+#define STM_TIM234_CCMR1_OC2CE 15
+#define STM_TIM234_CCMR1_OC2M 12
+#define STM_TIM234_CCMR1_OC2M_FROZEN 0
+#define STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH 1
+#define STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH 2
+#define STM_TIM234_CCMR1_OC2M_TOGGLE 3
+#define STM_TIM234_CCMR1_OC2M_FORCE_LOW 4
+#define STM_TIM234_CCMR1_OC2M_FORCE_HIGH 5
+#define STM_TIM234_CCMR1_OC2M_PWM_MODE_1 6
+#define STM_TIM234_CCMR1_OC2M_PWM_MODE_2 7
+#define STM_TIM234_CCMR1_OC2M_MASK 7UL
+#define STM_TIM234_CCMR1_OC2PE 11
+#define STM_TIM234_CCMR1_OC2FE 10
+#define STM_TIM234_CCMR1_CC2S 8
+#define STM_TIM234_CCMR1_CC2S_OUTPUT 0
+#define STM_TIM234_CCMR1_CC2S_INPUT_TI2 1
+#define STM_TIM234_CCMR1_CC2S_INPUT_TI1 2
+#define STM_TIM234_CCMR1_CC2S_INPUT_TRC 3
+#define STM_TIM234_CCMR1_CC2S_MASK 3UL
+
+#define STM_TIM234_CCMR1_OC1CE 7
+#define STM_TIM234_CCMR1_OC1M 4
+#define STM_TIM234_CCMR1_OC1M_FROZEN 0
+#define STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH 1
+#define STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH 2
+#define STM_TIM234_CCMR1_OC1M_TOGGLE 3
+#define STM_TIM234_CCMR1_OC1M_FORCE_LOW 4
+#define STM_TIM234_CCMR1_OC1M_FORCE_HIGH 5
+#define STM_TIM234_CCMR1_OC1M_PWM_MODE_1 6
+#define STM_TIM234_CCMR1_OC1M_PWM_MODE_2 7
+#define STM_TIM234_CCMR1_OC1M_MASK 7UL
+#define STM_TIM234_CCMR1_OC1PE 3
+#define STM_TIM234_CCMR1_OC1FE 2
+#define STM_TIM234_CCMR1_CC1S 0
+#define STM_TIM234_CCMR1_CC1S_OUTPUT 0
+#define STM_TIM234_CCMR1_CC1S_INPUT_TI1 1
+#define STM_TIM234_CCMR1_CC1S_INPUT_TI2 2
+#define STM_TIM234_CCMR1_CC1S_INPUT_TRC 3
+#define STM_TIM234_CCMR1_CC1S_MASK 3UL
+
+#define STM_TIM234_CCMR1_IC2F 12
+#define STM_TIM234_CCMR1_IC2F_NONE 0
+#define STM_TIM234_CCMR1_IC2F_CK_INT_N_2 1
+#define STM_TIM234_CCMR1_IC2F_CK_INT_N_4 2
+#define STM_TIM234_CCMR1_IC2F_CK_INT_N_8 3
+#define STM_TIM234_CCMR1_IC2F_DTS_2_N_6 4
+#define STM_TIM234_CCMR1_IC2F_DTS_2_N_8 5
+#define STM_TIM234_CCMR1_IC2F_DTS_4_N_6 6
+#define STM_TIM234_CCMR1_IC2F_DTS_4_N_8 7
+#define STM_TIM234_CCMR1_IC2F_DTS_8_N_6 8
+#define STM_TIM234_CCMR1_IC2F_DTS_8_N_8 9
+#define STM_TIM234_CCMR1_IC2F_DTS_16_N_5 10
+#define STM_TIM234_CCMR1_IC2F_DTS_16_N_6 11
+#define STM_TIM234_CCMR1_IC2F_DTS_16_N_8 12
+#define STM_TIM234_CCMR1_IC2F_DTS_32_N_5 13
+#define STM_TIM234_CCMR1_IC2F_DTS_32_N_6 14
+#define STM_TIM234_CCMR1_IC2F_DTS_32_N_8 15
+#define STM_TIM234_CCMR1_IC2PSC 10
+#define STM_TIM234_CCMR1_IC2PSC_NONE 0
+#define STM_TIM234_CCMR1_IC2PSC_2 1
+#define STM_TIM234_CCMR1_IC2PSC_4 2
+#define STM_TIM234_CCMR1_IC2PSC_8 3
+#define STM_TIM234_CCMR1_IC1F 4
+#define STM_TIM234_CCMR1_IC1F_NONE 0
+#define STM_TIM234_CCMR1_IC1F_CK_INT_N_2 1
+#define STM_TIM234_CCMR1_IC1F_CK_INT_N_4 2
+#define STM_TIM234_CCMR1_IC1F_CK_INT_N_8 3
+#define STM_TIM234_CCMR1_IC1F_DTS_2_N_6 4
+#define STM_TIM234_CCMR1_IC1F_DTS_2_N_8 5
+#define STM_TIM234_CCMR1_IC1F_DTS_4_N_6 6
+#define STM_TIM234_CCMR1_IC1F_DTS_4_N_8 7
+#define STM_TIM234_CCMR1_IC1F_DTS_8_N_6 8
+#define STM_TIM234_CCMR1_IC1F_DTS_8_N_8 9
+#define STM_TIM234_CCMR1_IC1F_DTS_16_N_5 10
+#define STM_TIM234_CCMR1_IC1F_DTS_16_N_6 11
+#define STM_TIM234_CCMR1_IC1F_DTS_16_N_8 12
+#define STM_TIM234_CCMR1_IC1F_DTS_32_N_5 13
+#define STM_TIM234_CCMR1_IC1F_DTS_32_N_6 14
+#define STM_TIM234_CCMR1_IC1F_DTS_32_N_8 15
+#define STM_TIM234_CCMR1_IC1PSC 2
+#define STM_TIM234_CCMR1_IC1PSC_NONE 0
+#define STM_TIM234_CCMR1_IC1PSC_2 1
+#define STM_TIM234_CCMR1_IC1PSC_4 2
+#define STM_TIM234_CCMR1_IC1PSC_8 3
+
+#define STM_TIM234_CCMR2_OC4CE 15
+#define STM_TIM234_CCMR2_OC4M 12
+#define STM_TIM234_CCMR2_OC4M_FROZEN 0
+#define STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH 1
+#define STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH 2
+#define STM_TIM234_CCMR2_OC4M_TOGGLE 3
+#define STM_TIM234_CCMR2_OC4M_FORCE_LOW 4
+#define STM_TIM234_CCMR2_OC4M_FORCE_HIGH 5
+#define STM_TIM234_CCMR2_OC4M_PWM_MODE_1 6
+#define STM_TIM234_CCMR2_OC4M_PWM_MODE_2 7
+#define STM_TIM234_CCMR2_OC4M_MASK 7UL
+#define STM_TIM234_CCMR2_OC4PE 11
+#define STM_TIM234_CCMR2_OC4FE 10
+#define STM_TIM234_CCMR2_CC4S 8
+#define STM_TIM234_CCMR2_CC4S_OUTPUT 0
+#define STM_TIM234_CCMR2_CC4S_INPUT_TI4 1
+#define STM_TIM234_CCMR2_CC4S_INPUT_TI3 2
+#define STM_TIM234_CCMR2_CC4S_INPUT_TRC 3
+#define STM_TIM234_CCMR2_CC4S_MASK 3UL
+
+#define STM_TIM234_CCMR2_OC3CE 7
+#define STM_TIM234_CCMR2_OC3M 4
+#define STM_TIM234_CCMR2_OC3M_FROZEN 0
+#define STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH 1
+#define STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH 2
+#define STM_TIM234_CCMR2_OC3M_TOGGLE 3
+#define STM_TIM234_CCMR2_OC3M_FORCE_LOW 4
+#define STM_TIM234_CCMR2_OC3M_FORCE_HIGH 5
+#define STM_TIM234_CCMR2_OC3M_PWM_MODE_1 6
+#define STM_TIM234_CCMR2_OC3M_PWM_MODE_2 7
+#define STM_TIM234_CCMR2_OC3M_MASK 7UL
+#define STM_TIM234_CCMR2_OC3PE 3
+#define STM_TIM234_CCMR2_OC3FE 2
+#define STM_TIM234_CCMR2_CC3S 0
+#define STM_TIM234_CCMR2_CC3S_OUTPUT 0
+#define STM_TIM234_CCMR2_CC3S_INPUT_TI3 1
+#define STM_TIM234_CCMR2_CC3S_INPUT_TI4 2
+#define STM_TIM234_CCMR2_CC3S_INPUT_TRC 3
+#define STM_TIM234_CCMR2_CC3S_MASK 3UL
+
+#define STM_TIM234_CCER_CC4NP 15
+#define STM_TIM234_CCER_CC4P 13
+#define STM_TIM234_CCER_CC4P_ACTIVE_HIGH 0
+#define STM_TIM234_CCER_CC4P_ACTIVE_LOW 1
+#define STM_TIM234_CCER_CC4E 12
+#define STM_TIM234_CCER_CC3NP 11
+#define STM_TIM234_CCER_CC3P 9
+#define STM_TIM234_CCER_CC3P_ACTIVE_HIGH 0
+#define STM_TIM234_CCER_CC3P_ACTIVE_LOW 1
+#define STM_TIM234_CCER_CC3E 8
+#define STM_TIM234_CCER_CC2NP 7
+#define STM_TIM234_CCER_CC2P 5
+#define STM_TIM234_CCER_CC2P_ACTIVE_HIGH 0
+#define STM_TIM234_CCER_CC2P_ACTIVE_LOW 1
+#define STM_TIM234_CCER_CC2E 4
+#define STM_TIM234_CCER_CC1NP 3
+#define STM_TIM234_CCER_CC1P 1
+#define STM_TIM234_CCER_CC1P_ACTIVE_HIGH 0
+#define STM_TIM234_CCER_CC1P_ACTIVE_LOW 1
+#define STM_TIM234_CCER_CC1E 0
+
+struct stm_tim67 {
+ vuint32_t cr1;
+ vuint32_t cr2;
+ uint32_t _unused_08;
+ vuint32_t dier;
+
+ vuint32_t sr;
+ vuint32_t egr;
+ uint32_t _unused_18;
+ uint32_t _unused_1c;
+
+ uint32_t _unused_20;
+ vuint32_t cnt;
+ vuint32_t psc;
+ vuint32_t arr;
+};
+
+extern struct stm_tim67 stm_tim6;
+
+#define STM_TIM67_CR1_ARPE (7)
+#define STM_TIM67_CR1_OPM (3)
+#define STM_TIM67_CR1_URS (2)
+#define STM_TIM67_CR1_UDIS (1)
+#define STM_TIM67_CR1_CEN (0)
+
+#define STM_TIM67_CR2_MMS (4)
+#define STM_TIM67_CR2_MMS_RESET 0
+#define STM_TIM67_CR2_MMS_ENABLE 1
+#define STM_TIM67_CR2_MMS_UPDATE 2
+#define STM_TIM67_CR2_MMS_MASK 7UL
+
+#define STM_TIM67_DIER_UDE (8)
+#define STM_TIM67_DIER_UIE (0)
+
+#define STM_TIM67_SR_UIF (0)
+
+#define STM_TIM67_EGR_UG (0)
#define isr_decl(name) void stm_ ## name ## _isr(void)
projects / fw / altos / blobdiff