#define STM_PUPDR_RESERVED 3
static inline void
-stm_pupdr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
+stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
gpio->pupdr = ((gpio->pupdr &
~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
value << STM_PUPDR_SHIFT(pin));
}
-static inline vuint32_t
+static inline uint32_t
stm_pupdr_get(struct stm_gpio *gpio, int pin) {
return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
}
}
static inline uint8_t
-stm_gpio_isset(struct stm_gpio *gpio, int pin) {
+stm_gpio_get(struct stm_gpio *gpio, int pin) {
return (gpio->idr >> pin) & 1;
}
#define STM_FLASH_ACR_PRFEN (1)
#define STM_FLASH_ACR_LATENCY (0)
+#define STM_FLASH_PECR_OBL_LAUNCH 18
+#define STM_FLASH_PECR_ERRIE 17
+#define STM_FLASH_PECR_EOPIE 16
+#define STM_FLASH_PECR_FPRG 10
+#define STM_FLASH_PECR_ERASE 9
+#define STM_FLASH_PECR_FTDW 8
+#define STM_FLASH_PECR_DATA 4
+#define STM_FLASH_PECR_PROG 3
+#define STM_FLASH_PECR_OPTLOCK 2
+#define STM_FLASH_PECR_PRGLOCK 1
+#define STM_FLASH_PECR_PELOCK 0
+
+#define STM_FLASH_SR_OPTVERR 11
+#define STM_FLASH_SR_SIZERR 10
+#define STM_FLASH_SR_PGAERR 9
+#define STM_FLASH_SR_WRPERR 8
+#define STM_FLASH_SR_READY 3
+#define STM_FLASH_SR_ENDHV 2
+#define STM_FLASH_SR_EOP 1
+#define STM_FLASH_SR_BSY 0
+
+#define STM_FLASH_PEKEYR_PEKEY1 0x89ABCDEF
+#define STM_FLASH_PEKEYR_PEKEY2 0x02030405
+
struct stm_rcc {
vuint32_t cr;
vuint32_t icscr;
struct stm_syscfg {
vuint32_t memrmp;
vuint32_t pmc;
- vuint32_t exticr1;
- vuint32_t exticr2;
- vuint32_t exticr3;
- vuint32_t exticr4;
+ vuint32_t exticr[4];
};
extern struct stm_syscfg stm_syscfg;
#define STM_SYSCFG_PMC_USB_PU 0
+#define STM_SYSCFG_EXTICR_PA 0
+#define STM_SYSCFG_EXTICR_PB 1
+#define STM_SYSCFG_EXTICR_PC 2
+#define STM_SYSCFG_EXTICR_PD 3
+#define STM_SYSCFG_EXTICR_PE 4
+#define STM_SYSCFG_EXTICR_PH 5
+
+static inline void
+stm_exticr_set(struct stm_gpio *gpio, int pin) {
+ uint8_t reg = pin >> 2;
+ uint8_t shift = (pin & 3) << 2;
+ uint8_t val = 0;
+
+ /* Enable SYSCFG */
+ stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGEN);
+
+ if (gpio == &stm_gpioa)
+ val = STM_SYSCFG_EXTICR_PA;
+ else if (gpio == &stm_gpiob)
+ val = STM_SYSCFG_EXTICR_PB;
+ else if (gpio == &stm_gpioc)
+ val = STM_SYSCFG_EXTICR_PC;
+ else if (gpio == &stm_gpiod)
+ val = STM_SYSCFG_EXTICR_PD;
+ else if (gpio == &stm_gpioe)
+ val = STM_SYSCFG_EXTICR_PE;
+
+ stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
+}
+
+
struct stm_dma_channel {
vuint32_t ccr;
vuint32_t cndtr;
#define STM_DMA_CHANNEL_USART2_TX 7
#define STM_DMA_CHANNEL_I2C2_TX 4
#define STM_DMA_CHANNEL_I2C2_RX 5
-#define STM_DMA_CHANNEL_I2C1_RX 6
-#define STM_DMA_CHANNEL_I2C1_TX 7
+#define STM_DMA_CHANNEL_I2C1_TX 6
+#define STM_DMA_CHANNEL_I2C1_RX 7
#define STM_DMA_CHANNEL_TIM2_CH3 1
#define STM_DMA_CHANNEL_TIM2_UP 2
#define STM_DMA_CHANNEL_TIM2_CH1 5
#define STM_I2C_CR2_FREQ_8_MHZ 8
#define STM_I2C_CR2_FREQ_16_MHZ 16
#define STM_I2C_CR2_FREQ_32_MHZ 32
-#define STM_I2C_CR2_FREQ_MASK 0x3f;
+#define STM_I2C_CR2_FREQ_MASK 0x3f
#define STM_I2C_SR1_SMBALERT 15
#define STM_I2C_SR1_TIMEOUT 14
#define STM_TIM234_CR1_CMS_CENTER_3 3
#define STM_TIM234_CR1_CMS_MASK 3
#define STM_TIM234_CR1_DIR 4
+#define STM_TIM234_CR1_DIR_UP 0
+#define STM_TIM234_CR1_DIR_DOWN 1
#define STM_TIM234_CR1_OPM 3
#define STM_TIM234_CR1_URS 2
#define STM_TIM234_CR1_UDIS 1
#define STM_TIM234_SMCR_ETF_MASK 15
#define STM_TIM234_SMCR_MSM 7
#define STM_TIM234_SMCR_TS 4
-#define STM_TIM234_SMCR_TS_TR0 0
-#define STM_TIM234_SMCR_TS_TR1 1
-#define STM_TIM234_SMCR_TS_TR2 2
-#define STM_TIM234_SMCR_TS_TR3 3
+#define STM_TIM234_SMCR_TS_ITR0 0
+#define STM_TIM234_SMCR_TS_ITR1 1
+#define STM_TIM234_SMCR_TS_ITR2 2
+#define STM_TIM234_SMCR_TS_ITR3 3
#define STM_TIM234_SMCR_TS_TI1F_ED 4
#define STM_TIM234_SMCR_TS_TI1FP1 5
#define STM_TIM234_SMCR_TS_TI2FP2 6
extern uint8_t stm_usb_sram[];
+struct stm_exti {
+ vuint32_t imr;
+ vuint32_t emr;
+ vuint32_t rtsr;
+ vuint32_t ftsr;
+
+ vuint32_t swier;
+ vuint32_t pr;
+};
+
+extern struct stm_exti stm_exti;
+
#endif /* _STM32L_H_ */