(0 << STM_SPI_CR1_RXONLY) |
(1 << STM_SPI_CR1_SSM) | /* Software SS handling */
(1 << STM_SPI_CR1_SSI) | /* ... */
- (0 << STM_SPI_CR1_LSBFIRST) | /* Little endian */
+ (0 << STM_SPI_CR1_LSBFIRST) | /* Big endian */
(1 << STM_SPI_CR1_SPE) | /* Enable SPI unit */
(STM_SPI_CR1_BR_PCLK_4 << STM_SPI_CR1_BR) | /* baud rate to pclk/4 */
(1 << STM_SPI_CR1_MSTR) |
stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SPI1EN);
ao_spi_channel_init(0);
-
- stm_nvic_set_enable(STM_ISR_SPI1_POS);
- stm_nvic_set_priority(STM_ISR_SPI1_POS, 3);
#endif
#if HAS_SPI_2
stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_SPI2EN);
ao_spi_channel_init(1);
-
- stm_nvic_set_enable(STM_ISR_SPI2_POS);
- stm_nvic_set_priority(STM_ISR_SPI2_POS, 3);
#endif
}