};
static uint8_t ao_spi_mutex[STM_NUM_SPI];
-static uint8_t ao_spi_index[STM_NUM_SPI];
+static uint8_t ao_spi_pin_config[STM_NUM_SPI];
static const struct ao_spi_stm_info ao_spi_stm_info[STM_NUM_SPI] = {
{
data,
len,
(0 << STM_DMA_CCR_MEM2MEM) |
- (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
+ (STM_DMA_CCR_PL_VERY_HIGH << STM_DMA_CCR_PL) |
(STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
(STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
(minc << STM_DMA_CCR_MINC) |
}
static void
-ao_spi_disable_index(uint8_t spi_index)
+ao_spi_disable_pin_config(uint8_t spi_pin_config)
{
/* Disable current config
*/
- switch (spi_index) {
+ switch (spi_pin_config) {
case AO_SPI_1_PA5_PA6_PA7:
stm_gpio_set(&stm_gpioa, 5, 1);
stm_moder_set(&stm_gpioa, 5, STM_MODER_OUTPUT);
}
static void
-ao_spi_enable_index(uint8_t spi_index)
+ao_spi_enable_pin_config(uint8_t spi_pin_config)
{
/* Enable new config
*/
- switch (spi_index) {
+ switch (spi_pin_config) {
case AO_SPI_1_PA5_PA6_PA7:
stm_afr_set(&stm_gpioa, 5, STM_AFR_AF5);
stm_afr_set(&stm_gpioa, 6, STM_AFR_AF5);
static void
ao_spi_config(uint8_t spi_index, uint32_t speed)
{
+ uint8_t spi_pin_config = AO_SPI_PIN_CONFIG(spi_index);
uint8_t id = AO_SPI_INDEX(spi_index);
struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
- if (spi_index != ao_spi_index[id]) {
+ if (spi_pin_config != ao_spi_pin_config[id]) {
/* Disable old config
*/
- ao_spi_disable_index(ao_spi_index[id]);
+ ao_spi_disable_pin_config(ao_spi_pin_config[id]);
/* Enable new config
*/
- ao_spi_enable_index(spi_index);
+ ao_spi_enable_pin_config(spi_pin_config);
/* Remember current config
*/
- ao_spi_index[id] = spi_index;
+ ao_spi_pin_config[id] = spi_pin_config;
}
+
+ /* Turn the SPI transceiver on and set the mode */
stm_spi->cr1 = ((0 << STM_SPI_CR1_BIDIMODE) | /* Three wire mode */
(0 << STM_SPI_CR1_BIDIOE) |
(0 << STM_SPI_CR1_CRCEN) | /* CRC disabled */
(1 << STM_SPI_CR1_SPE) | /* Enable SPI unit */
(speed << STM_SPI_CR1_BR) | /* baud rate to pclk/4 */
(1 << STM_SPI_CR1_MSTR) |
- (0 << STM_SPI_CR1_CPOL) | /* Format 0 */
- (0 << STM_SPI_CR1_CPHA));
+ (AO_SPI_CPOL(spi_index) << STM_SPI_CR1_CPOL) | /* Format */
+ (AO_SPI_CPHA(spi_index) << STM_SPI_CR1_CPHA));
validate_spi(stm_spi, 13, 0);
}
uint8_t id = AO_SPI_INDEX(spi_index);
struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
- ao_spi_disable_index(spi_index);
+ ao_spi_disable_pin_config(AO_SPI_PIN_CONFIG(spi_index));
stm_spi->cr1 = 0;
stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) |
stm_ospeedr_set(&stm_gpioe, 15, SPI_1_OSPEEDR);
# endif
stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SPI1EN);
- ao_spi_index[0] = AO_SPI_CONFIG_NONE;
+ ao_spi_pin_config[0] = AO_SPI_CONFIG_NONE;
ao_spi_channel_init(0);
#endif
stm_ospeedr_set(&stm_gpiod, 4, SPI_2_OSPEEDR);
# endif
stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_SPI2EN);
- ao_spi_index[1] = AO_SPI_CONFIG_NONE;
+ ao_spi_pin_config[1] = AO_SPI_CONFIG_NONE;
ao_spi_channel_init(1);
#endif
#if DEBUG