#define AO_SPI_INDEX(id) ((id) & AO_SPI_INDEX_MASK)
#define AO_SPI_CONFIG(id) ((id) & AO_SPI_CONFIG_MASK)
+uint8_t
+ao_spi_try_get(uint8_t spi_index, uint32_t speed, uint8_t task_id);
+
void
ao_spi_get(uint8_t spi_index, uint32_t speed);
ao_spi_put(uint8_t spi_index);
void
-ao_spi_send(void *block, uint16_t len, uint8_t spi_index);
+ao_spi_send(const void *block, uint16_t len, uint8_t spi_index);
void
ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
+void
+ao_spi_send_sync(void *block, uint16_t len, uint8_t spi_index);
+
+static inline void
+ao_spi_send_byte(uint8_t byte, uint8_t spi_index)
+{
+ struct stm_spi *stm_spi;
+
+ switch (AO_SPI_INDEX(spi_index)) {
+ case 0:
+ stm_spi = &stm_spi1;
+ break;
+ case 1:
+ stm_spi = &stm_spi2;
+ break;
+ }
+
+ stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) |
+ (0 << STM_SPI_CR2_RXNEIE) |
+ (0 << STM_SPI_CR2_ERRIE) |
+ (0 << STM_SPI_CR2_SSOE) |
+ (0 << STM_SPI_CR2_TXDMAEN) |
+ (0 << STM_SPI_CR2_RXDMAEN));
+
+ /* Clear RXNE */
+ (void) stm_spi->dr;
+
+ while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)));
+ stm_spi->dr = byte;
+}
+
void
ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
void
ao_spi_init(void);
+#define ao_spi_set_cs(reg,mask) ((reg)->bsrr = ((uint32_t) (mask)) << 16)
+#define ao_spi_clr_cs(reg,mask) ((reg)->bsrr = (mask))
+
#define ao_spi_get_mask(reg,mask,bus, speed) do { \
ao_spi_get(bus, speed); \
- (reg)->bsrr = ((uint32_t) mask) << 16; \
+ ao_spi_set_cs(reg,mask); \
} while (0)
+static inline uint8_t
+ao_spi_try_get_mask(struct stm_gpio *reg, uint16_t mask, uint8_t bus, uint32_t speed, uint8_t task_id)
+{
+ if (!ao_spi_try_get(bus, speed, task_id))
+ return 0;
+ ao_spi_set_cs(reg, mask);
+ return 1;
+}
+
#define ao_spi_put_mask(reg,mask,bus) do { \
- (reg)->bsrr = mask; \
+ ao_spi_clr_cs(reg,mask); \
ao_spi_put(bus); \
} while (0)
stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOEEN); \
} while (0)
+#define ao_disable_port(port) do { \
+ if ((port) == &stm_gpioa) \
+ stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOAEN); \
+ else if ((port) == &stm_gpiob) \
+ stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOBEN); \
+ else if ((port) == &stm_gpioc) \
+ stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOCEN); \
+ else if ((port) == &stm_gpiod) \
+ stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIODEN); \
+ else if ((port) == &stm_gpioe) \
+ stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOEEN); \
+ } while (0)
+
#define ao_gpio_set(port, bit, pin, v) stm_gpio_set(port, bit, v)
#define ao_gpio_get(port, bit, pin) stm_gpio_get(port, bit)
+#define ao_gpio_set_bits(port, bits) stm_gpio_set_bits(port, bits)
+
+#define ao_gpio_clr_bits(port, bits) stm_gpio_clr_bits(port, bits);
+
+
#define ao_enable_output(port,bit,pin,v) do { \
ao_enable_port(port); \
ao_gpio_set(port, bit, pin, v); \
stm_moder_set(port, bit, STM_MODER_OUTPUT);\
} while (0)
-#define ao_enable_input(port,bit,mode) do { \
- ao_enable_port(port); \
- stm_moder_set(port, bit, STM_MODER_INPUT); \
+#define ao_gpio_set_mode(port,bit,mode) do { \
if (mode == AO_EXTI_MODE_PULL_UP) \
stm_pupdr_set(port, bit, STM_PUPDR_PULL_UP); \
else if (mode == AO_EXTI_MODE_PULL_DOWN) \
else \
stm_pupdr_set(port, bit, STM_PUPDR_NONE); \
} while (0)
+
+#define ao_enable_input(port,bit,mode) do { \
+ ao_enable_port(port); \
+ stm_moder_set(port, bit, STM_MODER_INPUT); \
+ ao_gpio_set_mode(port, bit, mode); \
+ } while (0)
#define ao_enable_cs(port,bit) do { \
stm_gpio_set((port), bit, 1); \
#define ARM_PUSH32(stack, val) (*(--(stack)) = (val))
+typedef uint32_t ao_arch_irq_t;
+
static inline uint32_t
ao_arch_irqsave(void) {
uint32_t primask;
asm volatile("" ::: "memory");
}
+#if HAS_TASK
static inline void
ao_arch_init_stack(struct ao_task *task, void *start)
{
static inline void ao_arch_restore_stack(void) {
uint32_t sp;
+ uint32_t control;
+
+ asm("mrs %0,control" : "=&r" (control));
+ control |= (1 << 1);
+ asm("msr control,%0" : : "r" (control));
+ asm("isb");
+
sp = (uint32_t) ao_cur_task->sp;
/* Switch stacks */
/* Restore APSR */
asm("pop {r0}");
- asm("msr apsr,r0");
+ asm("msr apsr_nczvq,r0");
/* Restore general registers */
asm("pop {r0-r12,lr}\n");
asm("bx lr");
}
-#define ao_arch_isr_stack()
+#ifndef HAS_SAMPLE_PROFILE
+#define HAS_SAMPLE_PROFILE 0
+#endif
-#define ao_arch_wait_interrupt() do { \
- asm(".global ao_idle_loc\n\twfi\nao_idle_loc:"); \
- ao_arch_release_interrupts(); \
- ao_arch_block_interrupts(); \
- } while (0)
+#if DEBUG
+#define HAS_ARCH_VALIDATE_CUR_STACK 1
-#define ao_arch_critical(b) do { \
- ao_arch_block_interrupts(); \
- do { b } while (0); \
+static inline void
+ao_validate_cur_stack(void)
+{
+ uint8_t *psp;
+
+ asm("mrs %0,psp" : "=&r" (psp));
+ if (ao_cur_task &&
+ psp <= ao_cur_task->stack &&
+ psp >= ao_cur_task->stack - 256)
+ ao_panic(AO_PANIC_STACK);
+}
+#endif
+
+#if !HAS_SAMPLE_PROFILE
+#define HAS_ARCH_START_SCHEDULER 1
+
+static inline void ao_arch_start_scheduler(void) {
+ uint32_t sp;
+ uint32_t control;
+
+ asm("mrs %0,msp" : "=&r" (sp));
+ asm("msr psp,%0" : : "r" (sp));
+ asm("mrs %0,control" : "=&r" (control));
+ control |= (1 << 1);
+ asm("msr control,%0" : : "r" (control));
+ asm("isb");
+}
+#endif
+
+static inline void ao_arch_isr_stack(void) {
+ uint32_t control;
+
+ asm("mrs %0,control" : "=&r" (control));
+ control &= ~(1 << 1);
+ asm("msr control,%0" : : "r" (control));
+ asm("isb");
+}
+
+#endif
+
+#define ao_arch_wait_interrupt() do { \
+ asm("\twfi\n"); \
ao_arch_release_interrupts(); \
+ asm(".global ao_idle_loc\nao_idle_loc:"); \
+ ao_arch_block_interrupts(); \
+ } while (0)
+
+#define ao_arch_critical(b) do { \
+ uint32_t __mask = ao_arch_irqsave(); \
+ do { b } while (0); \
+ ao_arch_irqrestore(__mask); \
} while (0)
#endif /* _AO_ARCH_FUNCS_H_ */