#define AO_SPI_SPEED_200kHz AO_SPI_SPEED_125kHz
+#define AO_SPI_CPOL_BIT 4
+#define AO_SPI_CPHA_BIT 5
+
#define AO_SPI_CONFIG_1 0x00
#define AO_SPI_1_CONFIG_PA5_PA6_PA7 AO_SPI_CONFIG_1
#define AO_SPI_2_CONFIG_PB13_PB14_PB15 AO_SPI_CONFIG_1
#define AO_SPI_INDEX(id) ((id) & AO_SPI_INDEX_MASK)
#define AO_SPI_CONFIG(id) ((id) & AO_SPI_CONFIG_MASK)
+#define AO_SPI_PIN_CONFIG(id) ((id) & (AO_SPI_INDEX_MASK | AO_SPI_CONFIG_MASK))
+#define AO_SPI_CPOL(id) ((uint32_t) (((id) >> AO_SPI_CPOL_BIT) & 1))
+#define AO_SPI_CPHA(id) ((uint32_t) (((id) >> AO_SPI_CPHA_BIT) & 1))
+
+#define AO_SPI_MAKE_MODE(pol,pha) (((pol) << AO_SPI_CPOL_BIT) | ((pha) << AO_SPI_CPHA_BIT))
+#define AO_SPI_MODE_0 AO_SPI_MAKE_MODE(0,0)
+#define AO_SPI_MODE_1 AO_SPI_MAKE_MODE(0,1)
+#define AO_SPI_MODE_2 AO_SPI_MAKE_MODE(1,0)
+#define AO_SPI_MODE_3 AO_SPI_MAKE_MODE(1,1)
uint8_t
ao_spi_try_get(uint8_t spi_index, uint32_t speed, uint8_t task_id);
#endif
};
+void
+ao_debug_out(char c);
+
#if HAS_SERIAL_1
extern struct ao_stm_usart ao_stm_usart1;
#endif
}
static inline void
-ao_arch_memory_barrier() {
+ao_arch_memory_barrier(void) {
asm volatile("" ::: "memory");
}
static inline void
ao_arch_init_stack(struct ao_task *task, void *start)
{
- uint32_t *sp = (uint32_t *) ((void*) task->stack + AO_STACK_SIZE);
+ uint32_t *sp = &task->stack32[AO_STACK_SIZE>>2];
uint32_t a = (uint32_t) start;
int i;
/* BASEPRI with interrupts enabled */
ARM_PUSH32(sp, 0);
- task->sp = sp;
+ task->sp32 = sp;
}
static inline void ao_arch_save_regs(void) {
static inline void ao_arch_save_stack(void) {
uint32_t *sp;
asm("mov %0,sp" : "=&r" (sp) );
- ao_cur_task->sp = (sp);
+ ao_cur_task->sp32 = (sp);
}
static inline void ao_arch_restore_stack(void) {
/* Switch stacks */
- asm("mov sp, %0" : : "r" (ao_cur_task->sp) );
+ asm("mov sp, %0" : : "r" (ao_cur_task->sp32) );
#ifdef AO_NONMASK_INTERRUPTS
/* Restore BASEPRI */
ao_arch_irqrestore(__mask); \
} while (0)
+void start(void);
+
#endif /* _AO_ARCH_FUNCS_H_ */