#define LPC_IOCONF_FUNC_PIO0_3 0
#define LPC_IOCONF_FUNC_USB_VBUS 1
-/* PIO0_4
+/* PIO0_4 */
#define LPC_IOCONF_FUNC_PIO0_4 0
#define LPC_IOCONF_FUNC_I2C_SCL 1
/* PIO0_6 */
#define LPC_IOCONF_FUNC_PIO0_6 0
#define LPC_IOCONF_FUNC_USB_CONNECT 1
-#define LPC_IOCONF_FUNC_SCK0 2
+#define LPC_IOCONF_FUNC_PIO0_6_SCK0 2
/* PIO0_7 */
#define LPC_IOCONF_FUNC_PIO0_7 0
/* PIO0_10 */
#define LPC_IOCONF_FUNC_SWCLK 0
#define LPC_IOCONF_FUNC_PIO0_10 1
-#define LPC_IOCONF_FUNC_SCK0 2
+#define LPC_IOCONF_FUNC_PIO0_10_SCK0 2
#define LPC_IOCONF_FUNC_CT16B0_MAT2 3
/* PIO0_11 */
extern struct lpc_scb lpc_scb;
+#define LPC_SCB_SYSMEMREMAP_MAP 0
+# define LPC_SCB_SYSMEMREMAP_MAP_BOOT_LOADER 0
+# define LPC_SCB_SYSMEMREMAP_MAP_RAM 1
+# define LPC_SCB_SYSMEMREMAP_MAP_FLASH 2
+
#define LPC_SCB_PRESETCTRL_SSP0_RST_N 0
#define LPC_SCB_PRESETCTRL_I2C_RST_N 1
#define LPC_SCB_PRESETCTRL_SSP1_RST_N 2
#define LPC_SCB_CLKOUTUEN_ENA 0
+#define LPC_SCB_BOD_BODRSTLEV 0
+# define LPC_SCB_BOD_BODRSTLEV_1_46 0
+# define LPC_SCB_BOD_BODRSTLEV_2_06 1
+# define LPC_SCB_BOD_BODRSTLEV_2_35 2
+# define LPC_SCB_BOD_BODRSTLEV_2_63 3
+#define LPC_SCB_BOD_BODINTVAL 2
+# define LPC_SCB_BOD_BODINTVAL_RESERVED 0
+# define LPC_SCB_BOD_BODINTVAL_2_22 1
+# define LPC_SCB_BOD_BODINTVAL_2_52 2
+# define LPC_SCB_BOD_BODINTVAL_2_80 3
+#define LPC_SCB_BOD_BODRSTENA 4
+
#define LPC_SCB_PDRUNCFG_IRCOUT_PD 0
#define LPC_SCB_PDRUNCFG_IRC_PD 1
#define LPC_SCB_PDRUNCFG_FLASH_PD 2
static inline void
lpc_nvic_set_enable(int irq) {
- lpc_nvic.iser |= (1 << irq);
+ lpc_nvic.iser = (1 << irq);
}
static inline void
lpc_nvic_clear_enable(int irq) {
- lpc_nvic.icer |= (1 << irq);
+ lpc_nvic.icer = (1 << irq);
}
static inline int
#define LPC_ADC_CR_CLKS_6 5
#define LPC_ADC_CR_CLKS_5 6
#define LPC_ADC_CR_CLKS_4 7
+#define LPC_ADC_CR_START 24
+#define LPC_ADC_CR_START_NONE 0
+#define LPC_ADC_CR_START_NOW 1
+
+#define LPC_ADC_GDR_CHN 24
+#define LPC_ADC_GDR_OVERRUN 30
+#define LPC_ADC_GDR_DONE 31
#define LPC_ADC_INTEN_ADINTEN 0
#define LPC_ADC_INTEN_ADGINTEN 8
#define LPC_CT32B_PWMC_PWMEN2 2
#define LPC_CT32B_PWMC_PWMEN3 3
+#define LPC_CT32B_EMR_EMC0 4
+#define LPC_CT32B_EMR_EMC1 6
+#define LPC_CT32B_EMR_EMC2 8
+#define LPC_CT32B_EMR_EMC3 10
+
+#define LPC_CT32B_EMR_EMC_NOTHING 0
+#define LPC_CT32B_EMR_EMC_CLEAR 1
+#define LPC_CT32B_EMR_EMC_SET 2
+#define LPC_CT32B_EMR_EMC_TOGGLE 3
+
#endif /* _LPC_H_ */