--- /dev/null
+/* RX filter BW = 100.000000 */\r
+/* Address config = No address check */\r
+/* Packet length = 255 */\r
+/* Symbol rate = 38.3606 */\r
+/* PA ramping = false */\r
+/* Carrier frequency = 434.549988 */\r
+/* Bit rate = 38.3606 */\r
+/* Whitening = true */\r
+/* Manchester enable = false */\r
+/* Modulation format = 2-GFSK */\r
+/* Packet length mode = Variable */\r
+/* Device address = 0 */\r
+/* TX power = 15 */\r
+/* Deviation = 20.507812 */\r
+/***************************************************************\r
+ * SmartRF Studio(tm) Export\r
+ *\r
+ * Radio register settings specifed with address, value\r
+ *\r
+ * RF device: CC1120\r
+ *\r
+ ***************************************************************/\r
+\r
+\r
+ CC1120_SYNC3, 0x93, /* Sync Word Configuration [31:24] */\r
+ CC1120_SYNC2, 0x0b, /* Sync Word Configuration [23:16] */\r
+ CC1120_SYNC1, 0x51, /* Sync Word Configuration [15:8] */\r
+ CC1120_SYNC0, 0xde, /* Sync Word Configuration [7:0] */\r
+ CC1120_SYNC_CFG1, 0x08, /* Sync Word Detection Configuration */\r
+ CC1120_SYNC_CFG0, 0x17, /* Sync Word Length Configuration */\r
+ CC1120_DEVIATION_M, 0x50, /* Frequency Deviation Configuration */\r
+ CC1120_MODCFG_DEV_E, 0x0d, /* Modulation Format and Frequency Deviation Configuration */\r
+ CC1120_DCFILT_CFG, 0x1c, /* Digital DC Removal Configuration */\r
+ CC1120_PREAMBLE_CFG1, 0x18, /* Preamble Length Configuration */\r
+ CC1120_PREAMBLE_CFG0, 0x2a, /* */\r
+ CC1120_FREQ_IF_CFG, 0x40, /* RX Mixer Frequency Configuration */\r
+ CC1120_IQIC, 0x46, /* Digital Image Channel Compensation Configuration */\r
+ CC1120_CHAN_BW, 0x02, /* Channel Filter Configuration */\r
+ CC1120_MDMCFG1, 0x46, /* General Modem Parameter Configuration */\r
+ CC1120_MDMCFG0, 0x05, /* General Modem Parameter Configuration */\r
+ CC1120_DRATE2, 0x93, /* Data Rate Configuration Exponent and Mantissa [19:16] */\r
+ CC1120_DRATE1, 0xa4, /* Data Rate Configuration Mantissa [15:8] */\r
+ CC1120_DRATE0, 0x00, /* Data Rate Configuration Mantissa [7:0] */\r
+ CC1120_AGC_REF, 0x20, /* AGC Reference Level Configuration */\r
+ CC1120_AGC_CS_THR, 0x19, /* Carrier Sense Threshold Configuration */\r
+ CC1120_AGC_GAIN_ADJUST, 0x00, /* RSSI Offset Configuration */\r
+ CC1120_AGC_CFG3, 0x91, /* AGC Configuration */\r
+ CC1120_AGC_CFG2, 0x20, /* AGC Configuration */\r
+ CC1120_AGC_CFG1, 0xa9, /* AGC Configuration */\r
+ CC1120_AGC_CFG0, 0xcf, /* AGC Configuration */\r
+ CC1120_FIFO_CFG, 0x00, /* FIFO Configuration */\r
+ CC1120_DEV_ADDR, 0x00, /* Device Address Configuration */\r
+ CC1120_SETTLING_CFG, 0x03, /* Frequency Synthesizer Calibration and Settling Configuration */\r
+ CC1120_FS_CFG, 0x14, /* Frequency Synthesizer Configuration */\r
+ CC1120_WOR_CFG1, 0x08, /* eWOR Configuration, Reg 1 */\r
+ CC1120_WOR_CFG0, 0x21, /* eWOR Configuration, Reg 0 */\r
+ CC1120_WOR_EVENT0_MSB, 0x00, /* Event 0 Configuration */\r
+ CC1120_WOR_EVENT0_LSB, 0x00, /* Event 0 Configuration */\r
+ CC1120_PKT_CFG2, 0x04, /* Packet Configuration, Reg 2 */\r
+ CC1120_PKT_CFG1, 0x45, /* Packet Configuration, Reg 1 */\r
+ CC1120_PKT_CFG0, 0x20, /* Packet Configuration, Reg 0 */\r
+ CC1120_RFEND_CFG1, 0x0f, /* RFEND Configuration, Reg 1 */\r
+ CC1120_RFEND_CFG0, 0x00, /* RFEND Configuration, Reg 0 */\r
+ CC1120_PA_CFG2, 0x3f, /* Power Amplifier Configuration, Reg 2 */\r
+ CC1120_PA_CFG1, 0x56, /* Power Amplifier Configuration, Reg 1 */\r
+ CC1120_PA_CFG0, 0x7b, /* Power Amplifier Configuration, Reg 0 */\r
+ CC1120_PKT_LEN, 0xff, /* Packet Length Configuration */\r
+ CC1120_IF_MIX_CFG, 0x00, /* IF Mix Configuration */\r
+ CC1120_FREQOFF_CFG, 0x22, /* Frequency Offset Correction Configuration */\r
+ CC1120_TOC_CFG, 0x0b, /* Timing Offset Correction Configuration */\r
+ CC1120_MARC_SPARE, 0x00, /* MARC Spare */\r
+ CC1120_ECG_CFG, 0x00, /* External Clock Frequency Configuration */\r
+ CC1120_SOFT_TX_DATA_CFG, 0x00, /* Soft TX Data Configuration */\r
+ CC1120_EXT_CTRL, 0x01, /* External Control Configuration */\r
+ CC1120_RCCAL_FINE, 0x00, /* RC Oscillator Calibration (fine) */\r
+ CC1120_RCCAL_COARSE, 0x00, /* RC Oscillator Calibration (coarse) */\r
+ CC1120_RCCAL_OFFSET, 0x00, /* RC Oscillator Calibration Clock Offset */\r
+ CC1120_FREQOFF1, 0x00, /* Frequency Offset (MSB) */\r
+ CC1120_FREQOFF0, 0x00, /* Frequency Offset (LSB) */\r
+ CC1120_FREQ2, 0x6c, /* Frequency Configuration [23:16] */\r
+ CC1120_FREQ1, 0xa3, /* Frequency Configuration [15:8] */\r
+ CC1120_FREQ0, 0x33, /* Frequency Configuration [7:0] */\r
+ CC1120_IF_ADC2, 0x02, /* Analog to Digital Converter Configuration, Reg 2 */\r
+ CC1120_IF_ADC1, 0xa6, /* Analog to Digital Converter Configuration, Reg 1 */\r
+ CC1120_IF_ADC0, 0x04, /* Analog to Digital Converter Configuration, Reg 0 */\r
+ CC1120_FS_DIG1, 0x00, /* */\r
+ CC1120_FS_DIG0, 0x5f, /* */\r
+ CC1120_FS_CAL3, 0x00, /* */\r
+ CC1120_FS_CAL2, 0x20, /* */\r
+ CC1120_FS_CAL1, 0x40, /* */\r
+ CC1120_FS_CAL0, 0x0e, /* */\r
+ CC1120_FS_CHP, 0x28, /* Charge Pump Configuration */\r
+ CC1120_FS_DIVTWO, 0x03, /* Divide by 2 */\r
+ CC1120_FS_DSM1, 0x00, /* Digital Synthesizer Module Configuration, Reg 1 */\r
+ CC1120_FS_DSM0, 0x33, /* Digital Synthesizer Module Configuration, Reg 0 */\r
+ CC1120_FS_DVC1, 0xff, /* Divider Chain Configuration, Reg 1 */\r
+ CC1120_FS_DVC0, 0x17, /* Divider Chain Configuration, Reg 0 */\r
+ CC1120_FS_LBI, 0x00, /* Local Bias Configuration */\r
+ CC1120_FS_PFD, 0x50, /* Phase Frequency Detector Configuration */\r
+ CC1120_FS_PRE, 0x6e, /* Prescaler Configuration */\r
+ CC1120_FS_REG_DIV_CML, 0x14, /* */\r
+ CC1120_FS_SPARE, 0xac, /* */\r
+ CC1120_FS_VCO4, 0x14, /* VCO Configuration, Reg 4 */\r
+ CC1120_FS_VCO3, 0x00, /* VCO Configuration, Reg 3 */\r
+ CC1120_FS_VCO2, 0x00, /* VCO Configuration, Reg 2 */\r
+ CC1120_FS_VCO1, 0x00, /* VCO Configuration, Reg 1 */\r
+ CC1120_FS_VCO0, 0xb4, /* VCO Configuration, Reg 0 */\r
+ CC1120_GBIAS6, 0x00, /* Global Bias Configuration, Reg 6 */\r
+ CC1120_GBIAS5, 0x02, /* Global Bias Configuration, Reg 5 */\r
+ CC1120_GBIAS4, 0x00, /* Global Bias Configuration, Reg 4 */\r
+ CC1120_GBIAS3, 0x00, /* Global Bias Configuration, Reg 3 */\r
+ CC1120_GBIAS2, 0x10, /* Global Bias Configuration, Reg 2 */\r
+ CC1120_GBIAS1, 0x00, /* Global Bias Configuration, Reg 1 */\r
+ CC1120_GBIAS0, 0x00, /* Global Bias Configuration, Reg 0 */\r
+ CC1120_IFAMP, 0x01, /* Intermediate Frequency Amplifier Configuration */\r
+ CC1120_LNA, 0x01, /* Low Noise Amplifier Configuration */\r
+ CC1120_RXMIX, 0x01, /* RX Mixer Configuration */\r
+ CC1120_XOSC5, 0x0e, /* Crystal Oscillator Configuration, Reg 5 */\r
+ CC1120_XOSC4, 0xa0, /* Crystal Oscillator Configuration, Reg 4 */\r
+ CC1120_XOSC3, 0x03, /* Crystal Oscillator Configuration, Reg 3 */\r
+ CC1120_XOSC2, 0x04, /* Crystal Oscillator Configuration, Reg 2 */\r
+ CC1120_XOSC1, 0x01, /* Crystal Oscillator Configuration, Reg 1 */\r
+ CC1120_XOSC0, 0x00, /* Crystal Oscillator Configuration, Reg 0 */\r
+ CC1120_ANALOG_SPARE, 0x00, /* */\r
+ CC1120_PA_CFG3, 0x00, /* Power Amplifier Configuration, Reg 3 */\r
+ CC1120_WOR_TIME1, 0x00, /* eWOR Timer Status (MSB) */\r
+ CC1120_WOR_TIME0, 0x00, /* eWOR Timer Status (LSB) */\r
+ CC1120_WOR_CAPTURE1, 0x00, /* eWOR Timer Capture (MSB) */\r
+ CC1120_WOR_CAPTURE0, 0x00, /* eWOR Timer Capture (LSB) */\r
+ CC1120_BIST, 0x00, /* MARC BIST */\r
+ CC1120_DCFILTOFFSET_I1, 0x00, /* DC Filter Offset I (MSB) */\r
+ CC1120_DCFILTOFFSET_I0, 0x00, /* DC Filter Offset I (LSB) */\r
+ CC1120_DCFILTOFFSET_Q1, 0x00, /* DC Filter Offset Q (MSB) */\r
+ CC1120_DCFILTOFFSET_Q0, 0x00, /* DC Filter Offset Q (LSB) */\r
+ CC1120_IQIE_I1, 0x00, /* IQ Imbalance Value I (MSB) */\r
+ CC1120_IQIE_I0, 0x00, /* IQ Imbalance Value I (LSB) */\r
+ CC1120_IQIE_Q1, 0x00, /* IQ Imbalance Value Q (MSB) */\r
+ CC1120_IQIE_Q0, 0x00, /* IQ Imbalance Value Q (LSB) */\r
+ CC1120_RSSI1, 0x80, /* Received Signal Strength Indicator (MSB) */\r
+ CC1120_RSSI0, 0x00, /* Received Signal Strength Indicator (LSB) */\r
+ CC1120_MARCSTATE, 0x41, /* MARC State */\r
+ CC1120_LQI_VAL, 0x00, /* Link Quality Indicator Value */\r
+ CC1120_PQT_SYNC_ERR, 0xff, /* Preamble and Sync Word Error */\r
+ CC1120_DEM_STATUS, 0x00, /* Demodulator Status */\r
+ CC1120_FREQOFF_EST1, 0x00, /* Frequency Offset Estimate (MSB) */\r
+ CC1120_FREQOFF_EST0, 0x00, /* Frequency Offset Estimate (LSB) */\r
+ CC1120_AGC_GAIN3, 0x00, /* AGC Gain, Reg 3 */\r
+ CC1120_AGC_GAIN2, 0xd1, /* AGC Gain, Reg 2 */\r
+ CC1120_AGC_GAIN1, 0x00, /* AGC Gain, Reg 1 */\r
+ CC1120_AGC_GAIN0, 0x3f, /* AGC Gain, Reg 0 */\r
+ CC1120_SOFT_RX_DATA_OUT, 0x00, /* Soft Decision Symbol Data */\r
+ CC1120_SOFT_TX_DATA_IN, 0x00, /* Soft TX Data Input Register */\r
+ CC1120_ASK_SOFT_RX_DATA, 0x30, /* AGC ASK Soft Decision Output */\r
+ CC1120_RNDGEN, 0x7f, /* Random Number Value */\r
+ CC1120_MAGN2, 0x00, /* Signal Magnitude after CORDIC [16] */\r
+ CC1120_MAGN1, 0x00, /* Signal Magnitude after CORDIC [15:8] */\r
+ CC1120_MAGN0, 0x00, /* Signal Magnitude after CORDIC [7:0] */\r
+ CC1120_ANG1, 0x00, /* Signal Angular after CORDIC [9:8] */\r
+ CC1120_ANG0, 0x00, /* Signal Angular after CORDIC [7:0] */\r
+ CC1120_CHFILT_I2, 0x08, /* Channel Filter Data Real Part [18:16] */\r
+ CC1120_CHFILT_I1, 0x00, /* Channel Filter Data Real Part [15:8] */\r
+ CC1120_CHFILT_I0, 0x00, /* Channel Filter Data Real Part [7:0] */\r
+ CC1120_CHFILT_Q2, 0x00, /* Channel Filter Data Imaginary Part [18:16] */\r
+ CC1120_CHFILT_Q1, 0x00, /* Channel Filter Data Imaginary Part [15:8] */\r
+ CC1120_CHFILT_Q0, 0x00, /* Channel Filter Data Imaginary Part [7:0] */\r
+ CC1120_GPIO_STATUS, 0x00, /* GPIO Status */\r
+ CC1120_FSCAL_CTRL, 0x01, /* */\r
+ CC1120_PHASE_ADJUST, 0x00, /* */\r
+ CC1120_PARTNUMBER, 0x00, /* Part Number */\r
+ CC1120_PARTVERSION, 0x00, /* Part Revision */\r
+ CC1120_SERIAL_STATUS, 0x00, /* Serial Status */\r
+ CC1120_RX_STATUS, 0x01, /* RX Status */\r
+ CC1120_TX_STATUS, 0x00, /* TX Status */\r
+ CC1120_MARC_STATUS1, 0x00, /* MARC Status, Reg 1 */\r
+ CC1120_MARC_STATUS0, 0x00, /* MARC Status, Reg 0 */\r
+ CC1120_PA_IFAMP_TEST, 0x00, /* */\r
+ CC1120_FSRF_TEST, 0x00, /* */\r
+ CC1120_PRE_TEST, 0x00, /* */\r
+ CC1120_PRE_OVR, 0x00, /* */\r
+ CC1120_ADC_TEST, 0x00, /* ADC Test */\r
+ CC1120_DVC_TEST, 0x0b, /* DVC Test */\r
+ CC1120_ATEST, 0x40, /* */\r
+ CC1120_ATEST_LVDS, 0x00, /* */\r
+ CC1120_ATEST_MODE, 0x00, /* */\r
+ CC1120_XOSC_TEST1, 0x3c, /* */\r
+ CC1120_XOSC_TEST0, 0x00, /* */\r
+ CC1120_RXFIRST, 0x00, /* RX FIFO Pointer (first entry) */\r
+ CC1120_TXFIRST, 0x00, /* TX FIFO Pointer (first entry) */\r
+ CC1120_RXLAST, 0x00, /* RX FIFO Pointer (last entry) */\r
+ CC1120_TXLAST, 0x00, /* TX FIFO Pointer (last entry) */\r
+\r
projects / fw / altos / blobdiff