#define P2SEL_PRI3P1_MASK (1 << 6)
#define P2SEL_PRI2P1_USART1 (0 << 5)
#define P2SEL_PRI2P1_TIMER3 (1 << 5)
+#define P2SEL_PRI2P1_MASK (1 << 5)
#define P2SEL_PRI1P1_TIMER1 (0 << 4)
#define P2SEL_PRI1P1_TIMER4 (1 << 4)
+#define P2SEL_PRI1P1_MASK (1 << 4)
#define P2SEL_PRI0P1_USART0 (0 << 3)
#define P2SEL_PRI0P1_TIMER1 (1 << 3)
+#define P2SEL_PRI0P1_MASK (1 << 3)
#define P2SEL_SELP2_4_GPIO (0 << 2)
#define P2SEL_SELP2_4_PERIPHERAL (1 << 2)
+#define P2SEL_SELP2_4_MASK (1 << 2)
#define P2SEL_SELP2_3_GPIO (0 << 1)
#define P2SEL_SELP2_3_PERIPHERAL (1 << 1)
+#define P2SEL_SELP2_3_MASK (1 << 1)
#define P2SEL_SELP2_0_GPIO (0 << 0)
#define P2SEL_SELP2_0_PERIPHERAL (1 << 0)
#define P2SEL_SELP2_0_MASK (1 << 0)
#define P0IFG_USB_RESUME (1 << 7)
+sfr at 0x8C PICTL;
+#define PICTL_P2IEN (1 << 5)
+#define PICTL_P0IENH (1 << 4)
+#define PICTL_P0IENL (1 << 3)
+#define PICTL_P2ICON (1 << 2)
+#define PICTL_P1ICON (1 << 1)
+#define PICTL_P0ICON (1 << 0)
+
/* GPIO pins */
sfr at 0x80 P0;