work in progress

[fw/sdcc] / sim / ucsim / xa.src / inst_gen.cc

diff --git a/sim/ucsim/xa.src/inst_gen.cc b/sim/ucsim/xa.src/inst_gen.cc
index 1b621719aa4fef5982fb02f87d1a3cd5d28cde7c..3deab22bc0bbbb254848b6424053b6a68cc3ab1b 100644 (file)
--- a/sim/ucsim/xa.src/inst_gen.cc
+++ b/sim/ucsim/xa.src/inst_gen.cc
@@ -4,11 +4,12 @@
    of inst.cc with FUNC1 and FUNC2 defined as
    various operations to implement ADD, ADDC, ...
  *
- * Written by Karl Bongers karl@turbobit.com
- *
- * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * Copyright (C) 1999,2002 Drotos Daniel, Talker Bt.
  * 
  * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ * Other contributors include:
+ *   Karl Bongers karl@turbobit.com,
+ *   Johan Knol 
  *
  */
 
@@ -125,7 +126,6 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
                       )
                 );
       } else {
-        int offset = (int)((short)fetch2());
         set_reg1( RI_F0,
                   FUNC1( reg1(RI_F0),
                         get1(reg2(RI_07)+offset)
@@ -172,11 +172,23 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
     break;
 
     case REG_DATA8 :
+#if 0
+      {
+        unsigned char dat = fetch();
+        unsigned char res;
+        res = FUNC1( reg1(RI_F0), dat);
+        set_reg1( RI_F0, res );
+   printf("reg_data8 code=%x dat=%x, res=%x r=%x\n", code, dat, res, reg1( RI_F0) );
+      }
+#endif
       set_reg1( RI_F0, FUNC1( reg1(RI_F0), fetch()) );
     break;
 
     case REG_DATA16 :
-      set_reg2( RI_F0, FUNC2( reg2(RI_F0), fetch2()) );
+      {
+        unsigned short dat = fetch2();
+        set_reg2( RI_F0, FUNC2( reg2(RI_F0), dat) );
+      }
     break;
 
     case IREGINC_DATA8 :