0.2.38-pre1 implements AVR instructions

[fw/sdcc] / sim / ucsim / avr.src / avr.cc

diff --git a/sim/ucsim/avr.src/avr.cc b/sim/ucsim/avr.src/avr.cc
index 950bd824cbd5ac4f383d526e812437cb1d440f69..6e330f5bf0c2e352d6b8bc1ea04c5235b26b4a55 100644 (file)
--- a/sim/ucsim/avr.src/avr.cc
+++ b/sim/ucsim/avr.src/avr.cc
@@ -53,6 +53,7 @@ cl_avr::cl_avr(class cl_sim *asim):
   cl_uc(asim)
 {
   type= CPU_AVR;
+  sleep_executed= 0;
 }
 
 int
@@ -84,7 +85,8 @@ cl_avr::get_mem_size(enum mem_class type)
     case MEM_IRAM: return(0x10000);
     default: return(0);
     }
- return(cl_uc::get_mem_size(type));
+  //return(0);
+  //return(cl_uc::get_mem_size(type));
 }
 
 int
@@ -471,6 +473,8 @@ cl_avr::exec_inst(void)
        return(ijmp(code));
       if ((code & 0xff00) == 0x9600)
        return(adiw_Rdl_K(code));
+      if ((code & 0xff00) == 0x9700)
+       return(sbiw_Rdl_K(code));
       switch (code & 0xfc00)
        {
        case 0x9000:
@@ -571,6 +575,91 @@ cl_avr::exec_inst(void)
 }
 
 
+/*
+ */
+
+int
+cl_avr::push_data(t_mem data)
+{
+  t_addr sp;
+  t_mem spl, sph;
+  
+  spl= ram->read(SPL);
+  sph= ram->read(SPH);
+  sp= 0xffff & (256*sph + spl);
+  ram->write(sp, &data);
+  sp= 0xffff & (sp-1);
+  spl= sp & 0xff;
+  sph= (sp>>8) & 0xff;
+  ram->write(SPL, &spl);
+  ram->write(SPH, &sph);
+  return(resGO);
+}
+
+int
+cl_avr::push_addr(t_addr addr)
+{
+  t_addr sp;
+  t_mem spl, sph, al, ah;
+  
+  spl= ram->read(SPL);
+  sph= ram->read(SPH);
+  sp= 0xffff & (256*sph + spl);
+  al= addr & 0xff;
+  ah= (addr>>8) & 0xff;
+  ram->write(sp, &ah);
+  sp= 0xffff & (sp-1);
+  ram->write(sp, &al);
+  sp= 0xffff & (sp-1);
+  spl= sp & 0xff;
+  sph= (sp>>8) & 0xff;
+  ram->write(SPL, &spl);
+  ram->write(SPH, &sph);
+  return(resGO);
+}
+
+int
+cl_avr::pop_data(t_mem *data)
+{
+  t_addr sp;
+  t_mem spl, sph;
+
+  spl= ram->read(SPL);
+  sph= ram->read(SPH);
+  sp= 256*sph + spl;
+  sp= 0xffff & (sp+1);
+  *data= ram->read(sp);
+  spl= sp & 0xff;
+  sph= (sp>>8) & 0xff;
+  ram->write(SPL, &spl);
+  ram->write(SPH, &sph);
+
+  return(resGO);
+}
+
+int
+cl_avr::pop_addr(t_addr *addr)
+{
+  t_addr sp;
+  t_mem spl, sph, al, ah;
+
+  spl= ram->read(SPL);
+  sph= ram->read(SPH);
+  sp= 256*sph + spl;
+  sp= 0xffff & (sp+1);
+  al= ram->read(sp);
+  sp= 0xffff & (sp+1);
+  ah= ram->read(sp);
+  *addr= ah*256 + al;
+  spl= sp & 0xff;
+  sph= (sp>>8) & 0xff;
+  ram->write(SPL, &spl);
+  ram->write(SPH, &sph);
+  
+  return(resGO);
+}
+
+
 /*
  * Set Z, N, V, S bits of SREG after logic instructions and some others
  */