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explicitly do not include frontsilk in the zip file .. the refdes info is not
[hw/telemini]
/
telemini.pcb
diff --git
a/telemini.pcb
b/telemini.pcb
index 9f4e52f4992850d0ff012f9e469773b2699e60d4..d12ba1ea09e4d079a4820ba71b8a2d4a3feb47d5 100644
(file)
--- a/
telemini.pcb
+++ b/
telemini.pcb
@@
-1,5
+1,5
@@
# release: pcb 20100929
# release: pcb 20100929
-# date:
Fri May 13 15:11:33
2011
+# date:
Sun Jun 5 20:09:17
2011
# user: bdale (Bdale Garbee,KB0G)
# host: rover
# user: bdale (Bdale Garbee,KB0G)
# host: rover
@@
-1718,9
+1718,10
@@
Layer(3 "outline")
Layer(4 "silk")
(
Text[127215 35422 3 100 "` 2011" "auto"]
Layer(4 "silk")
(
Text[127215 35422 3 100 "` 2011" "auto"]
- Text[134093 42768 3 100 "TeleMini v
0.2
" "auto"]
+ Text[134093 42768 3 100 "TeleMini v
1.0
" "auto"]
Text[121400 43400 3 100 "Bdale Garbee" "auto"]
Text[35000 44500 3 100 "apogee main" "auto"]
Text[121400 43400 3 100 "Bdale Garbee" "auto"]
Text[35000 44500 3 100 "apogee main" "auto"]
+ Text[63100 13500 0 100 "pwr" "clearline,auto"]
Polygon("clearpoly")
(
[134800 34000] [149100 34000] [149100 16000] [134800 16000]
Polygon("clearpoly")
(
[134800 34000] [149100 34000] [149100 16000] [134800 16000]