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Merge branch 'master' of ssh://git.gag.com/scm/git/fw/altos
[fw/altos]
/
src
/
stmf0
/
ao_timer.c
diff --git
a/src/stmf0/ao_timer.c
b/src/stmf0/ao_timer.c
index 58e52995cf32f35cbb4146b092f60e6217771972..b7047e10b9e89ce240b52aabb0723d52dd7a7505 100644
(file)
--- a/
src/stmf0/ao_timer.c
+++ b/
src/stmf0/ao_timer.c
@@
-60,12
+60,9
@@
void stm_systick_isr(void)
{
if (stm_systick.csr & (1 << STM_SYSTICK_CSR_COUNTFLAG)) {
++ao_tick_count;
{
if (stm_systick.csr & (1 << STM_SYSTICK_CSR_COUNTFLAG)) {
++ao_tick_count;
-#if HAS_TASK_QUEUE
- if (ao_task_alarm_tick && (int16_t) (ao_tick_count - ao_task_alarm_tick) >= 0)
- ao_task_check_alarm((uint16_t) ao_tick_count);
-#endif
+ ao_task_check_alarm();
#if AO_DATA_ALL
#if AO_DATA_ALL
- if (++ao_data_count == ao_data_interval) {
+ if (++ao_data_count == ao_data_interval
&& ao_data_interval
) {
ao_data_count = 0;
#if HAS_ADC
#if HAS_FAKE_FLIGHT
ao_data_count = 0;
#if HAS_ADC
#if HAS_FAKE_FLIGHT
@@
-186,7
+183,7
@@
ao_clock_normal_start(void)
#if AO_HSE_BYPASS
stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
#else
#if AO_HSE_BYPASS
stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
#else
- stm_rcc.cr &= ~(1 << STM_RCC_CR_HSEBYP);
+ stm_rcc.cr &= ~(1
UL
<< STM_RCC_CR_HSEBYP);
#endif
/* Enable HSE clock */
stm_rcc.cr |= (1 << STM_RCC_CR_HSEON);
#endif
/* Enable HSE clock */
stm_rcc.cr |= (1 << STM_RCC_CR_HSEON);
@@
-194,8
+191,8
@@
ao_clock_normal_start(void)
asm("nop");
/* Disable the PLL */
asm("nop");
/* Disable the PLL */
- stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON);
- while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))
+ stm_rcc.cr &= ~(1
UL
<< STM_RCC_CR_PLLON);
+ while (stm_rcc.cr & (1
UL
<< STM_RCC_CR_PLLRDY))
asm("nop");
/* Set multiplier */
asm("nop");
/* Set multiplier */
@@
-204,7
+201,7
@@
ao_clock_normal_start(void)
cfgr |= (AO_RCC_CFGR_PLLMUL << STM_RCC_CFGR_PLLMUL);
/* PLL source */
cfgr |= (AO_RCC_CFGR_PLLMUL << STM_RCC_CFGR_PLLMUL);
/* PLL source */
- cfgr &= ~(1 << STM_RCC_CFGR_PLLSRC);
+ cfgr &= ~(1
UL
<< STM_RCC_CFGR_PLLSRC);
cfgr |= (STM_RCC_CFGR_PLLSRC_TARGET_CLOCK << STM_RCC_CFGR_PLLSRC);
stm_rcc.cfgr = cfgr;
cfgr |= (STM_RCC_CFGR_PLLSRC_TARGET_CLOCK << STM_RCC_CFGR_PLLSRC);
stm_rcc.cfgr = cfgr;
@@
-264,7
+261,7
@@
ao_clock_normal_switch(void)
}
#if !AO_HSI && !AO_NEED_HSI
/* Turn off the HSI clock */
}
#if !AO_HSI && !AO_NEED_HSI
/* Turn off the HSI clock */
- stm_rcc.cr &= ~(1 << STM_RCC_CR_HSION);
+ stm_rcc.cr &= ~(1
UL
<< STM_RCC_CR_HSION);
#endif
#ifdef STM_PLLSRC
/* USB PLL source */
#endif
#ifdef STM_PLLSRC
/* USB PLL source */
@@
-294,9
+291,6
@@
ao_clock_init(void)
/* Enable 1 wait state so the CPU can run at 48MHz */
stm_flash.acr |= (STM_FLASH_ACR_LATENCY_1 << STM_FLASH_ACR_LATENCY);
/* Enable 1 wait state so the CPU can run at 48MHz */
stm_flash.acr |= (STM_FLASH_ACR_LATENCY_1 << STM_FLASH_ACR_LATENCY);
- /* Enable power interface clock */
- stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
-
/* HCLK to 48MHz -> AHB prescaler = /1 */
cfgr = stm_rcc.cfgr;
cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);
/* HCLK to 48MHz -> AHB prescaler = /1 */
cfgr = stm_rcc.cfgr;
cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);