-
-#define STM_ADC_SQ_TEMP 16
-#define STM_ADC_SQ_V_REF 17
-
-#define STM_ADC_SR_JCNR 9
-#define STM_ADC_SR_RCNR 8
-#define STM_ADC_SR_ADONS 6
-#define STM_ADC_SR_OVR 5
-#define STM_ADC_SR_STRT 4
-#define STM_ADC_SR_JSTRT 3
-#define STM_ADC_SR_JEOC 2
-#define STM_ADC_SR_EOC 1
-#define STM_ADC_SR_AWD 0
-
-#define STM_ADC_CR1_OVRIE 26
-#define STM_ADC_CR1_RES 24
-#define STM_ADC_CR1_RES_12 0
-#define STM_ADC_CR1_RES_10 1
-#define STM_ADC_CR1_RES_8 2
-#define STM_ADC_CR1_RES_6 3
-#define STM_ADC_CR1_RES_MASK 3
-#define STM_ADC_CR1_AWDEN 23
-#define STM_ADC_CR1_JAWDEN 22
-#define STM_ADC_CR1_PDI 17
-#define STM_ADC_CR1_PDD 16
-#define STM_ADC_CR1_DISCNUM 13
-#define STM_ADC_CR1_DISCNUM_1 0
-#define STM_ADC_CR1_DISCNUM_2 1
-#define STM_ADC_CR1_DISCNUM_3 2
-#define STM_ADC_CR1_DISCNUM_4 3
-#define STM_ADC_CR1_DISCNUM_5 4
-#define STM_ADC_CR1_DISCNUM_6 5
-#define STM_ADC_CR1_DISCNUM_7 6
-#define STM_ADC_CR1_DISCNUM_8 7
-#define STM_ADC_CR1_DISCNUM_MASK 7
-#define STM_ADC_CR1_JDISCEN 12
-#define STM_ADC_CR1_DISCEN 11
-#define STM_ADC_CR1_JAUTO 10
-#define STM_ADC_CR1_AWDSGL 9
-#define STM_ADC_CR1_SCAN 8
-#define STM_ADC_CR1_JEOCIE 7
-#define STM_ADC_CR1_AWDIE 6
-#define STM_ADC_CR1_EOCIE 5
-#define STM_ADC_CR1_AWDCH 0
-#define STM_ADC_CR1_AWDCH_MASK 0x1f
-
-#define STM_ADC_CR2_SWSTART 30
-#define STM_ADC_CR2_EXTEN 28
-#define STM_ADC_CR2_EXTEN_DISABLE 0
-#define STM_ADC_CR2_EXTEN_RISING 1
-#define STM_ADC_CR2_EXTEN_FALLING 2
-#define STM_ADC_CR2_EXTEN_BOTH 3
-#define STM_ADC_CR2_EXTEN_MASK 3
-#define STM_ADC_CR2_EXTSEL 24
-#define STM_ADC_CR2_EXTSEL_TIM9_CC2 0
-#define STM_ADC_CR2_EXTSEL_TIM9_TRGO 1
-#define STM_ADC_CR2_EXTSEL_TIM2_CC3 2
-#define STM_ADC_CR2_EXTSEL_TIM2_CC2 3
-#define STM_ADC_CR2_EXTSEL_TIM3_TRGO 4
-#define STM_ADC_CR2_EXTSEL_TIM4_CC4 5
-#define STM_ADC_CR2_EXTSEL_TIM2_TRGO 6
-#define STM_ADC_CR2_EXTSEL_TIM3_CC1 7
-#define STM_ADC_CR2_EXTSEL_TIM3_CC3 8
-#define STM_ADC_CR2_EXTSEL_TIM4_TRGO 9
-#define STM_ADC_CR2_EXTSEL_TIM6_TRGO 10
-#define STM_ADC_CR2_EXTSEL_EXTI_11 15
-#define STM_ADC_CR2_EXTSEL_MASK 15
-#define STM_ADC_CR2_JWSTART 22
-#define STM_ADC_CR2_JEXTEN 20
-#define STM_ADC_CR2_JEXTEN_DISABLE 0
-#define STM_ADC_CR2_JEXTEN_RISING 1
-#define STM_ADC_CR2_JEXTEN_FALLING 2
-#define STM_ADC_CR2_JEXTEN_BOTH 3
-#define STM_ADC_CR2_JEXTEN_MASK 3
-#define STM_ADC_CR2_JEXTSEL 16
-#define STM_ADC_CR2_JEXTSEL_TIM9_CC1 0
-#define STM_ADC_CR2_JEXTSEL_TIM9_TRGO 1
-#define STM_ADC_CR2_JEXTSEL_TIM2_TRGO 2
-#define STM_ADC_CR2_JEXTSEL_TIM2_CC1 3
-#define STM_ADC_CR2_JEXTSEL_TIM3_CC4 4
-#define STM_ADC_CR2_JEXTSEL_TIM4_TRGO 5
-#define STM_ADC_CR2_JEXTSEL_TIM4_CC1 6
-#define STM_ADC_CR2_JEXTSEL_TIM4_CC2 7
-#define STM_ADC_CR2_JEXTSEL_TIM4_CC3 8
-#define STM_ADC_CR2_JEXTSEL_TIM10_CC1 9
-#define STM_ADC_CR2_JEXTSEL_TIM7_TRGO 10
-#define STM_ADC_CR2_JEXTSEL_EXTI_15 15
-#define STM_ADC_CR2_JEXTSEL_MASK 15
-#define STM_ADC_CR2_ALIGN 11
-#define STM_ADC_CR2_EOCS 10
-#define STM_ADC_CR2_DDS 9
-#define STM_ADC_CR2_DMA 8
-#define STM_ADC_CR2_DELS 4
-#define STM_ADC_CR2_DELS_NONE 0
-#define STM_ADC_CR2_DELS_UNTIL_READ 1
-#define STM_ADC_CR2_DELS_7 2
-#define STM_ADC_CR2_DELS_15 3
-#define STM_ADC_CR2_DELS_31 4
-#define STM_ADC_CR2_DELS_63 5
-#define STM_ADC_CR2_DELS_127 6
-#define STM_ADC_CR2_DELS_255 7
-#define STM_ADC_CR2_DELS_MASK 7
-#define STM_ADC_CR2_CONT 1
-#define STM_ADC_CR2_ADON 0
-
-#define STM_ADC_CCR_TSVREFE 23
-#define STM_ADC_CCR_ADCPRE 16
-#define STM_ADC_CCR_ADCPRE_HSI_1 0
-#define STM_ADC_CCR_ADCPRE_HSI_2 1
-#define STM_ADC_CCR_ADCPRE_HSI_4 2
-#define STM_ADC_CCR_ADCPRE_MASK 3
-
-struct stm_temp_cal {
- uint16_t vref;
- uint16_t ts_cal_cold;
- uint16_t reserved;
- uint16_t ts_cal_hot;
+#define stm_adc (*(struct stm_adc *) 0x40012400)
+
+#define STM_ADC_ISR_AWD 7
+#define STM_ADC_ISR_OVR 4
+#define STM_ADC_ISR_EOSEQ 3
+#define STM_ADC_ISR_EOC 2
+#define STM_ADC_ISR_EOSMP 1
+#define STM_ADC_ISR_ADRDY 0
+
+#define STM_ADC_IER_AWDIE 7
+#define STM_ADC_IER_OVRIE 4
+#define STM_ADC_IER_EOSEQIE 3
+#define STM_ADC_IER_EOCIE 2
+#define STM_ADC_IER_EOSMPIE 1
+#define STM_ADC_IER_ADRDYIE 0
+
+#define STM_ADC_CR_ADCAL 31
+#define STM_ADC_CR_ADVREGEN 28
+#define STM_ADC_CR_ADSTP 4
+#define STM_ADC_CR_ADSTART 2
+#define STM_ADC_CR_ADDIS 1
+#define STM_ADC_CR_ADEN 0
+
+#define STM_ADC_CFGR1_AWDCH 26
+#define STM_ADC_CFGR1_AWDEN 23
+#define STM_ADC_CFGR1_AWDSGL 22
+#define STM_ADC_CFGR1_DISCEN 16
+#define STM_ADC_CFGR1_AUTOOFF 15
+#define STM_ADC_CFGR1_WAIT 14
+#define STM_ADC_CFGR1_CONT 13
+#define STM_ADC_CFGR1_OVRMOD 12
+#define STM_ADC_CFGR1_EXTEN 10
+#define STM_ADC_CFGR1_EXTEN_DISABLE 0
+#define STM_ADC_CFGR1_EXTEN_RISING 1
+#define STM_ADC_CFGR1_EXTEN_FALLING 2
+#define STM_ADC_CFGR1_EXTEN_BOTH 3
+#define STM_ADC_CFGR1_EXTEN_MASK 3
+
+#define STM_ADC_CFGR1_EXTSEL 6
+#define STM_ADC_CFGR1_ALIGN 5
+#define STM_ADC_CFGR1_RES 3
+#define STM_ADC_CFGR1_RES_12 0
+#define STM_ADC_CFGR1_RES_10 1
+#define STM_ADC_CFGR1_RES_8 2
+#define STM_ADC_CFGR1_RES_6 3
+#define STM_ADC_CFGR1_RES_MASK 3
+#define STM_ADC_CFGR1_SCANDIR 2
+#define STM_ADC_CFGR1_SCANDIR_UP 0
+#define STM_ADC_CFGR1_SCANDIR_DOWN 1
+#define STM_ADC_CFGR1_DMACFG 1
+#define STM_ADC_CFGR1_DMACFG_ONESHOT 0
+#define STM_ADC_CFGR1_DMACFG_CIRCULAR 1
+#define STM_ADC_CFGR1_DMAEN 0
+
+#define STM_ADC_CFGR2_CKMODE 30
+#define STM_ADC_CFGR2_CKMODE_ADCCLK 0
+#define STM_ADC_CFGR2_CKMODE_PCLK_2 1
+#define STM_ADC_CFGR2_CKMODE_PCLK_4 2
+#define STM_ADC_CFGR2_CKMODE_PCLK 3
+
+#define STM_ADC_SMPR_SMP 0
+#define STM_ADC_SMPR_SMP_1_5 0
+#define STM_ADC_SMPR_SMP_7_5 1
+#define STM_ADC_SMPR_SMP_13_5 2
+#define STM_ADC_SMPR_SMP_28_5 3
+#define STM_ADC_SMPR_SMP_41_5 4
+#define STM_ADC_SMPR_SMP_55_5 5
+#define STM_ADC_SMPR_SMP_71_5 6
+#define STM_ADC_SMPR_SMP_239_5 7
+
+#define STM_ADC_TR_HT 16
+#define STM_ADC_TR_LT 0
+
+#define STM_ADC_CCR_LFMEN 25
+#define STM_ADC_CCR_VLCDEN 24
+#define STM_ADC_CCR_TSEN 23
+#define STM_ADC_CCR_VREFEN 22
+#define STM_ADC_CCR_PRESC 18
+
+#define STM_ADC_CHSEL_TEMP 18
+#define STM_ADC_CHSEL_VREF 17
+#define STM_ADC_CHSEL_VLCD 16
+
+struct stm_cal {
+ uint16_t ts_cal_cold; /* 30°C */
+ uint16_t vrefint_cal;
+ uint16_t unused_c0;
+ uint16_t ts_cal_hot; /* 110°C */