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altos/arm: Align data so that gcc 5.4 doesn't do byte-accesses. Add -Wcast-align
[fw/altos]
/
src
/
stm
/
stm32l.h
diff --git
a/src/stm/stm32l.h
b/src/stm/stm32l.h
index c5c28e76a584f9d62b831b37c730aee4fdca8f6b..be1e1d65112c6c47f7b65ee1b3be7bc9934c2472 100644
(file)
--- a/
src/stm/stm32l.h
+++ b/
src/stm/stm32l.h
@@
-3,7
+3,8
@@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
@@
-166,6
+167,16
@@
stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
}
gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
}
+static inline void
+stm_gpio_set_bits(struct stm_gpio *gpio, uint16_t bits) {
+ gpio->bsrr = bits;
+}
+
+static inline void
+stm_gpio_clr_bits(struct stm_gpio *gpio, uint16_t bits) {
+ gpio->bsrr = ((uint32_t) bits) << 16;
+}
+
static inline uint8_t
stm_gpio_get(struct stm_gpio *gpio, int pin) {
return (gpio->idr >> pin) & 1;
static inline uint8_t
stm_gpio_get(struct stm_gpio *gpio, int pin) {
return (gpio->idr >> pin) & 1;
@@
-1349,10
+1360,13
@@
extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
#define STM_SPI_CR2_TXDMAEN 1
#define STM_SPI_CR2_RXDMAEN 0
#define STM_SPI_CR2_TXDMAEN 1
#define STM_SPI_CR2_RXDMAEN 0
+#define STM_SPI_SR_FRE 8
#define STM_SPI_SR_BSY 7
#define STM_SPI_SR_OVR 6
#define STM_SPI_SR_MODF 5
#define STM_SPI_SR_CRCERR 4
#define STM_SPI_SR_BSY 7
#define STM_SPI_SR_OVR 6
#define STM_SPI_SR_MODF 5
#define STM_SPI_SR_CRCERR 4
+#define STM_SPI_SR_UDR 3
+#define STM_SPI_SR_CHSIDE 2
#define STM_SPI_SR_TXE 1
#define STM_SPI_SR_RXNE 0
#define STM_SPI_SR_TXE 1
#define STM_SPI_SR_RXNE 0
@@
-1515,7
+1529,7
@@
extern struct stm_dbg_mcu stm_dbg_mcu;
static inline uint16_t
stm_dev_id(void) {
static inline uint16_t
stm_dev_id(void) {
- return stm_dbgmcu.idcode & 0xfff;
+ return stm_dbg
_
mcu.idcode & 0xfff;
}
struct stm_flash_size {
}
struct stm_flash_size {
@@
-1775,7
+1789,7
@@
extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
#define STM_TIM234_CCMR1_OC1M_PWM_MODE_1 6
#define STM_TIM234_CCMR1_OC1M_PWM_MODE_2 7
#define STM_TIM234_CCMR1_OC1M_MASK 7
#define STM_TIM234_CCMR1_OC1M_PWM_MODE_1 6
#define STM_TIM234_CCMR1_OC1M_PWM_MODE_2 7
#define STM_TIM234_CCMR1_OC1M_MASK 7
-#define STM_TIM234_CCMR1_OC1PE
11
+#define STM_TIM234_CCMR1_OC1PE
3
#define STM_TIM234_CCMR1_OC1FE 2
#define STM_TIM234_CCMR1_CC1S 0
#define STM_TIM234_CCMR1_CC1S_OUTPUT 0
#define STM_TIM234_CCMR1_OC1FE 2
#define STM_TIM234_CCMR1_CC1S 0
#define STM_TIM234_CCMR1_CC1S_OUTPUT 0
@@
-1815,7
+1829,7
@@
extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
#define STM_TIM234_CCMR2_OC3M_PWM_MODE_1 6
#define STM_TIM234_CCMR2_OC3M_PWM_MODE_2 7
#define STM_TIM234_CCMR2_OC3M_MASK 7
#define STM_TIM234_CCMR2_OC3M_PWM_MODE_1 6
#define STM_TIM234_CCMR2_OC3M_PWM_MODE_2 7
#define STM_TIM234_CCMR2_OC3M_MASK 7
-#define STM_TIM234_CCMR2_OC3PE
11
+#define STM_TIM234_CCMR2_OC3PE
3
#define STM_TIM234_CCMR2_OC3FE 2
#define STM_TIM234_CCMR2_CC3S 0
#define STM_TIM234_CCMR2_CC3S_OUTPUT 0
#define STM_TIM234_CCMR2_OC3FE 2
#define STM_TIM234_CCMR2_CC3S 0
#define STM_TIM234_CCMR2_CC3S_OUTPUT 0
@@
-1947,7
+1961,7
@@
union stm_usb_bdt {
#define STM_USB_BDT_SIZE 8
#define STM_USB_BDT_SIZE 8
-extern uint8_t stm_usb_sram[];
+extern uint8_t stm_usb_sram[]
__attribute__ ((aligned(4)))
;
struct stm_exti {
vuint32_t imr;
struct stm_exti {
vuint32_t imr;