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altos: add button matrix driver
[fw/altos]
/
src
/
stm
/
stm32l.h
diff --git
a/src/stm/stm32l.h
b/src/stm/stm32l.h
index 352214ffdbc055c50c8fb44a3cde16dee23ea8d8..a20efa8a1b0c31f52bfa5536752f607d36ad4b3a 100644
(file)
--- a/
src/stm/stm32l.h
+++ b/
src/stm/stm32l.h
@@
-3,7
+3,8
@@
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
@@
-517,7
+518,7
@@
extern struct stm_rcc stm_rcc;
#define STM_RCC_CFGR_MCOPRE_DIV_4 2
#define STM_RCC_CFGR_MCOPRE_DIV_8 3
#define STM_RCC_CFGR_MCOPRE_DIV_16 4
#define STM_RCC_CFGR_MCOPRE_DIV_4 2
#define STM_RCC_CFGR_MCOPRE_DIV_8 3
#define STM_RCC_CFGR_MCOPRE_DIV_16 4
-#define STM_RCC_CFGR_MCOPRE_
DIV_MASK
7
+#define STM_RCC_CFGR_MCOPRE_
MASK
7
#define STM_RCC_CFGR_MCOSEL (24)
#define STM_RCC_CFGR_MCOSEL_DISABLE 0
#define STM_RCC_CFGR_MCOSEL (24)
#define STM_RCC_CFGR_MCOSEL_DISABLE 0
@@
-896,7
+897,11
@@
struct stm_nvic {
vuint32_t sc; /* 0xc10 0xe000ed10 System Control Register */
vuint32_t cc; /* 0xc14 0xe000ed14 Configuration Control Register */
vuint32_t sc; /* 0xc10 0xe000ed10 System Control Register */
vuint32_t cc; /* 0xc14 0xe000ed14 Configuration Control Register */
- uint8_t _unusedc18[0xe00 - 0xc18];
+ vuint32_t shpr7_4; /* 0xc18 0xe000ed18 System Hander Priority Registers */
+ vuint32_t shpr11_8; /* 0xc1c */
+ vuint32_t shpr15_12; /* 0xc20 */
+
+ uint8_t _unusedc18[0xe00 - 0xc24];
vuint32_t stir; /* 0xe00 */
};
vuint32_t stir; /* 0xe00 */
};
@@
-1593,6
+1598,7
@@
extern struct stm_i2c stm_i2c1, stm_i2c2;
#define STM_I2C_CR2_FREQ_4_MHZ 4
#define STM_I2C_CR2_FREQ_8_MHZ 8
#define STM_I2C_CR2_FREQ_16_MHZ 16
#define STM_I2C_CR2_FREQ_4_MHZ 4
#define STM_I2C_CR2_FREQ_8_MHZ 8
#define STM_I2C_CR2_FREQ_16_MHZ 16
+#define STM_I2C_CR2_FREQ_24_MHZ 24
#define STM_I2C_CR2_FREQ_32_MHZ 32
#define STM_I2C_CR2_FREQ_MASK 0x3f
#define STM_I2C_CR2_FREQ_32_MHZ 32
#define STM_I2C_CR2_FREQ_MASK 0x3f
@@
-1739,6
+1745,12
@@
extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
#define STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK 7
#define STM_TIM234_SMCR_SMS_MASK 7
#define STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK 7
#define STM_TIM234_SMCR_SMS_MASK 7
+#define STM_TIM234_DIER_CC4IE 4
+#define STM_TIM234_DIER_CC3IE 3
+#define STM_TIM234_DIER_CC2IE 2
+#define STM_TIM234_DIER_CC1IE 1
+#define STM_TIM234_DIER_UIE 0
+
#define STM_TIM234_SR_CC4OF 12
#define STM_TIM234_SR_CC3OF 11
#define STM_TIM234_SR_CC2OF 10
#define STM_TIM234_SR_CC4OF 12
#define STM_TIM234_SR_CC3OF 11
#define STM_TIM234_SR_CC2OF 10
@@
-1839,15
+1851,23
@@
extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
#define STM_TIM234_CCER_CC4NP 15
#define STM_TIM234_CCER_CC4P 13
#define STM_TIM234_CCER_CC4NP 15
#define STM_TIM234_CCER_CC4P 13
+#define STM_TIM234_CCER_CC4P_ACTIVE_HIGH 0
+#define STM_TIM234_CCER_CC4P_ACTIVE_LOW 1
#define STM_TIM234_CCER_CC4E 12
#define STM_TIM234_CCER_CC3NP 11
#define STM_TIM234_CCER_CC3P 9
#define STM_TIM234_CCER_CC4E 12
#define STM_TIM234_CCER_CC3NP 11
#define STM_TIM234_CCER_CC3P 9
+#define STM_TIM234_CCER_CC3P_ACTIVE_HIGH 0
+#define STM_TIM234_CCER_CC3P_ACTIVE_LOW 1
#define STM_TIM234_CCER_CC3E 8
#define STM_TIM234_CCER_CC2NP 7
#define STM_TIM234_CCER_CC2P 5
#define STM_TIM234_CCER_CC3E 8
#define STM_TIM234_CCER_CC2NP 7
#define STM_TIM234_CCER_CC2P 5
+#define STM_TIM234_CCER_CC2P_ACTIVE_HIGH 0
+#define STM_TIM234_CCER_CC2P_ACTIVE_LOW 1
#define STM_TIM234_CCER_CC2E 4
#define STM_TIM234_CCER_CC1NP 3
#define STM_TIM234_CCER_CC1P 1
#define STM_TIM234_CCER_CC2E 4
#define STM_TIM234_CCER_CC1NP 3
#define STM_TIM234_CCER_CC1P 1
+#define STM_TIM234_CCER_CC1P_ACTIVE_HIGH 0
+#define STM_TIM234_CCER_CC1P_ACTIVE_LOW 1
#define STM_TIM234_CCER_CC1E 0
struct stm_usb {
#define STM_TIM234_CCER_CC1E 0
struct stm_usb {
@@
-1960,7
+1980,7
@@
union stm_usb_bdt {
#define STM_USB_BDT_SIZE 8
#define STM_USB_BDT_SIZE 8
-extern uint8_t stm_usb_sram[];
+extern uint8_t stm_usb_sram[]
__attribute__ ((aligned(4)))
;
struct stm_exti {
vuint32_t imr;
struct stm_exti {
vuint32_t imr;