+ out_cr2("send enable isr", stm_i2c,
+ AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN));
+ while ((in_sr1("send_btf", stm_i2c) & (1 << STM_I2C_SR1_BTF)) == 0)
+ if (ao_sleep(&ao_i2c_state[index]))
+ break;
+ out_cr2("send disable isr", stm_i2c, AO_STM_I2C_CR2);
+ sei();
+ if (stop) {
+ out_cr1("stop", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
+ ao_i2c_wait_stop(index);
+ }
+ return TRUE;
+}
+
+void
+ao_i2c_recv_dma_isr(int index)
+{
+ int i;
+ struct stm_i2c *stm_i2c = NULL;
+
+ for (i = 0; i < STM_NUM_I2C; i++)
+ if (index == ao_i2c_stm_info[i].rx_dma_index) {
+ stm_i2c = ao_i2c_stm_info[i].stm_i2c;
+ break;
+ }
+ if (!stm_i2c)
+ return;
+ stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_LAST);
+ ao_dma_done[index] = 1;
+ ao_wakeup(&ao_dma_done[index]);
+}
+
+uint8_t
+ao_i2c_recv(void *block, uint16_t len, uint8_t index, uint8_t stop)
+{
+ struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
+ uint8_t *b = block;
+ int t;
+ uint8_t ret = TRUE;
+
+ if (len == 0)
+ return TRUE;
+ if (len == 1) {
+ ao_i2c_recv_data[index] = block;
+ ao_i2c_recv_len[index] = 1;
+ out_cr1("setup recv 1", stm_i2c, AO_STM_I2C_CR1);
+
+ /* Clear any pending ADDR bit */
+ in_sr2("clear addr", stm_i2c);
+
+ /* Enable interrupts to transfer the byte */
+ out_cr2("setup recv 1", stm_i2c,
+ AO_STM_I2C_CR2 |
+ (1 << STM_I2C_CR2_ITEVTEN) |
+ (1 << STM_I2C_CR2_ITERREN) |
+ (1 << STM_I2C_CR2_ITBUFEN));
+ if (stop)
+ out_cr1("setup recv 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
+
+ ao_alarm(1);
+ cli();
+ while (ao_i2c_recv_len[index])
+ if (ao_sleep(&ao_i2c_recv_len[index]))
+ break;
+ sei();
+ ret = ao_i2c_recv_len[index] == 0;
+ ao_clear_alarm();
+ } else {
+ uint8_t rx_dma_index = ao_i2c_stm_info[index].rx_dma_index;
+ ao_dma_set_transfer(rx_dma_index,
+ &stm_i2c->dr,
+ block,
+ len,
+ (0 << STM_DMA_CCR_MEM2MEM) |
+ (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
+ (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
+ (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
+ (1 << STM_DMA_CCR_MINC) |
+ (0 << STM_DMA_CCR_PINC) |
+ (0 << STM_DMA_CCR_CIRC) |
+ (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
+ out_cr1("recv > 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_ACK));
+ out_cr2("recv > 1", stm_i2c, AO_STM_I2C_CR2 |
+ (1 << STM_I2C_CR2_DMAEN) | (1 << STM_I2C_CR2_LAST));
+ /* Clear any pending ADDR bit */
+ in_sr2("clear addr", stm_i2c);
+
+ ao_dma_start(rx_dma_index);
+ ao_alarm(len);
+ cli();
+ while (!ao_dma_done[rx_dma_index])
+ if (ao_sleep(&ao_dma_done[rx_dma_index]))
+ break;
+ sei();
+ ao_clear_alarm();
+ ret = ao_dma_done[rx_dma_index];
+ ao_dma_done_transfer(rx_dma_index);
+ out_cr1("stop recv > 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
+ }
+ if (stop)
+ ao_i2c_wait_stop(index);
+ return ret;