+static uint8_t
+ao_radio_get_marc_status(void)
+{
+ return ao_radio_reg_read(CC1120_MARC_STATUS1);
+}
+
+static void
+ao_radio_mcu_wakeup_isr(void)
+{
+ ao_radio_mcu_wake = 1;
+ ao_wakeup(&ao_radio_wake);
+}
+
+
+static void
+ao_radio_check_marc_status(void)
+{
+ ao_radio_mcu_wake = 0;
+ ao_radio_marc_status = ao_radio_get_marc_status();
+
+ /* Anyt other than 'tx/rx finished' means an error occurred */
+ if (ao_radio_marc_status & ~(CC1120_MARC_STATUS1_TX_FINISHED|CC1120_MARC_STATUS1_RX_FINISHED))
+ ao_radio_abort = 1;
+ if (ao_radio_marc_status & (CC1120_MARC_STATUS1_TX_FINISHED))
+ ao_radio_tx_finished = 1;
+}
+
+static void
+ao_radio_isr(void)
+{
+ ao_exti_disable(AO_CC1120_INT_PORT, AO_CC1120_INT_PIN);
+ ao_radio_wake = 1;
+ ao_wakeup(&ao_radio_wake);
+}
+
+static void
+ao_radio_start_tx(void)
+{
+ ao_exti_set_callback(AO_CC1120_INT_PORT, AO_CC1120_INT_PIN, ao_radio_isr);
+ ao_exti_enable(AO_CC1120_INT_PORT, AO_CC1120_INT_PIN);
+ ao_exti_enable(AO_CC1120_MCU_WAKEUP_PORT, AO_CC1120_MCU_WAKEUP_PIN);
+ ao_radio_tx_finished = 0;
+ ao_radio_strobe(CC1120_STX);
+}
+
+static void
+ao_radio_idle(void)
+{
+ for (;;) {
+ uint8_t state = (ao_radio_strobe(CC1120_SIDLE) >> CC1120_STATUS_STATE) & CC1120_STATUS_STATE_MASK;
+ if (state == CC1120_STATUS_STATE_IDLE)
+ break;
+ if (state == CC1120_STATUS_STATE_TX_FIFO_ERROR)
+ ao_radio_strobe(CC1120_SFTX);
+ if (state == CC1120_STATUS_STATE_RX_FIFO_ERROR)
+ ao_radio_strobe(CC1120_SFRX);
+ }
+ /* Flush any pending TX bytes */
+ ao_radio_strobe(CC1120_SFTX);
+}
+
+/*
+ * Packet deviation is 20.5kHz
+ *
+ * fdev = fosc >> 24 * (256 + dev_m) << dev_e
+ *
+ * 32e6Hz / (2 ** 24) * (256 + 80) * (2 ** 5) = 20508Hz
+ */
+
+#define PACKET_DEV_E 5
+#define PACKET_DEV_M 80
+
+/*
+ * For our packet data
+ *
+ * (2**20 + DATARATE_M) * 2 ** DATARATE_E
+ * Rdata = -------------------------------------- * fosc
+ * 2 ** 39
+ *
+ * Symbol rate 38400 Baud:
+ *
+ * DATARATE_M = 239914
+ * DATARATE_E = 9
+ * CHANBW = 74.42 (round to 100)
+ *
+ * Symbol rate 9600 Baud:
+ *
+ * DATARATE_M = 239914
+ * DATARATE_E = 7
+ * CHANBW = 58.58 (round to 62.5)
+ *
+ * Symbol rate 2400 Baud:
+ *
+ * DATARATE_M = 239914
+ * DATARATE_E = 5
+ * CHANBW = 47.61 (round to 50)
+ */
+
+#define PACKET_DRATE_M 239914
+
+#define PACKET_DRATE_E_384 9
+#define PACKET_CHAN_BW_384 0x02 /* 200 / 2 = 100 */
+
+#define PACKET_DRATE_E_96 7
+#define PACKET_CHAN_BW_96 0x42 /* 125 / 2 = 62.5 */
+
+#define PACKET_DRATE_E_24 5
+#define PACKET_CHAN_BW_24 0x04 /* 200 / 4 = 50 */
+
+static const uint16_t packet_setup[] = {
+ CC1120_DEVIATION_M, PACKET_DEV_M,
+ CC1120_MODCFG_DEV_E, ((CC1120_MODCFG_DEV_E_MODEM_MODE_NORMAL << CC1120_MODCFG_DEV_E_MODEM_MODE) |
+ (CC1120_MODCFG_DEV_E_MOD_FORMAT_2_GFSK << CC1120_MODCFG_DEV_E_MOD_FORMAT) |
+ (PACKET_DEV_E << CC1120_MODCFG_DEV_E_DEV_E)),
+ CC1120_DRATE1, ((PACKET_DRATE_M >> 8) & 0xff),
+ CC1120_DRATE0, ((PACKET_DRATE_M >> 0) & 0xff),
+ CC1120_PKT_CFG2, ((CC1120_PKT_CFG2_CCA_MODE_ALWAYS_CLEAR << CC1120_PKT_CFG2_CCA_MODE) |
+ (CC1120_PKT_CFG2_PKT_FORMAT_NORMAL << CC1120_PKT_CFG2_PKT_FORMAT)),
+ CC1120_PKT_CFG1, ((0 << CC1120_PKT_CFG1_WHITE_DATA) |
+ (CC1120_PKT_CFG1_ADDR_CHECK_CFG_NONE << CC1120_PKT_CFG1_ADDR_CHECK_CFG) |
+ (CC1120_PKT_CFG1_CRC_CFG_DISABLED << CC1120_PKT_CFG1_CRC_CFG) |
+ (0 << CC1120_PKT_CFG1_APPEND_STATUS)),
+ CC1120_PKT_CFG0, ((0 << CC1120_PKT_CFG0_RESERVED7) |
+ (CC1120_PKT_CFG0_LENGTH_CONFIG_FIXED << CC1120_PKT_CFG0_LENGTH_CONFIG) |
+ (0 << CC1120_PKT_CFG0_PKG_BIT_LEN) |
+ (0 << CC1120_PKT_CFG0_UART_MODE_EN) |
+ (0 << CC1120_PKT_CFG0_UART_SWAP_EN)),
+ CC1120_PREAMBLE_CFG1, ((CC1120_PREAMBLE_CFG1_NUM_PREAMBLE_4_BYTES << CC1120_PREAMBLE_CFG1_NUM_PREAMBLE) |
+ (CC1120_PREAMBLE_CFG1_PREAMBLE_WORD_AA << CC1120_PREAMBLE_CFG1_PREAMBLE_WORD)),
+ AO_CC1120_MARC_GPIO_IOCFG, CC1120_IOCFG_GPIO_CFG_MARC_MCU_WAKEUP,
+};
+
+static const uint16_t packet_setup_384[] = {
+ CC1120_DRATE2, ((PACKET_DRATE_E_384 << CC1120_DRATE2_DATARATE_E) |
+ (((PACKET_DRATE_M >> 16) & CC1120_DRATE2_DATARATE_M_19_16_MASK) << CC1120_DRATE2_DATARATE_M_19_16)),
+ CC1120_CHAN_BW, PACKET_CHAN_BW_384,
+ CC1120_PA_CFG0, 0x7b,
+};
+
+static const uint16_t packet_setup_96[] = {
+ CC1120_DRATE2, ((PACKET_DRATE_E_96 << CC1120_DRATE2_DATARATE_E) |
+ (((PACKET_DRATE_M >> 16) & CC1120_DRATE2_DATARATE_M_19_16_MASK) << CC1120_DRATE2_DATARATE_M_19_16)),
+ CC1120_CHAN_BW, PACKET_CHAN_BW_96,
+ CC1120_PA_CFG0, 0x7d,
+};
+
+static const uint16_t packet_setup_24[] = {
+ CC1120_DRATE2, ((PACKET_DRATE_E_24 << CC1120_DRATE2_DATARATE_E) |
+ (((PACKET_DRATE_M >> 16) & CC1120_DRATE2_DATARATE_M_19_16_MASK) << CC1120_DRATE2_DATARATE_M_19_16)),
+ CC1120_CHAN_BW, PACKET_CHAN_BW_24,
+ CC1120_PA_CFG0, 0x7e,
+};
+
+static const uint16_t packet_tx_setup[] = {
+ CC1120_PKT_CFG2, ((CC1120_PKT_CFG2_CCA_MODE_ALWAYS_CLEAR << CC1120_PKT_CFG2_CCA_MODE) |
+ (CC1120_PKT_CFG2_PKT_FORMAT_NORMAL << CC1120_PKT_CFG2_PKT_FORMAT)),
+ AO_CC1120_INT_GPIO_IOCFG, CC1120_IOCFG_GPIO_CFG_RX0TX1_CFG,
+};
+
+static const uint16_t packet_rx_setup[] = {
+ CC1120_PKT_CFG2, ((CC1120_PKT_CFG2_CCA_MODE_ALWAYS_CLEAR << CC1120_PKT_CFG2_CCA_MODE) |
+ (CC1120_PKT_CFG2_PKT_FORMAT_SYNCHRONOUS_SERIAL << CC1120_PKT_CFG2_PKT_FORMAT)),
+ AO_CC1120_INT_GPIO_IOCFG, CC1120_IOCFG_GPIO_CFG_CLKEN_SOFT,
+};
+