+#if MULTI_SPI
+
+#define SPI_BUF(bus) ((bus) ? SPI_BUF_1 : SPI_BUF_0)
+#define SPI_CSR(bus) ((bus) ? SPI_CSR_1 : SPI_CSR_0)
+#define SPI_BAUD(bus) ((bus) ? SPI_BAUD_1 : SPI_BAUD_0)
+#define SPI_GCR(bus) ((bus) ? SPI_GCR_1 : SPI_GCR_0)
+#define SPI_CFG_MASK(bus) ((bus) ? SPI_CFG_MASK_1 : SPI_CFG_MASK_0)
+#define SPI_DMA_TX(bus) ((bus) ? SPI_DMA_TX_1 : SPI_DMA_TX_0)
+#define SPI_DMA_RX(bus) ((bus) ? SPI_DMA_RX_1 : SPI_DMA_RX_0)
+#define SPI_CFG(bus) ((bus) ? SPI_CFG_1 : SPI_CFG_0)
+#define SPI_SEL(bus) ((bus) ? SPI_SEL_1 : SPI_SEL_0)
+#define SPI_BITS(bus) ((bus) ? SPI_BITS_1 : SPI_BITS_0)
+#define SPI_CSS_BIT(bus) ((bus) ? SPI_CSS_BIT_1 : SPI_CSS_BIT_0)
+
+#else
+
+#if HAS_SPI_0
+#define SPI_BUF(bus) SPI_BUF_0
+#define SPI_CSR(bus) SPI_CSR_0
+#define SPI_BAUD(bus) SPI_BAUD_0
+#define SPI_GCR(bus) SPI_GCR_0
+#define SPI_CFG_MASK(bus) SPI_CFG_MASK_0
+#define SPI_DMA_TX(bus) SPI_DMA_TX_0
+#define SPI_DMA_RX(bus) SPI_DMA_RX_0
+#define SPI_CFG(bus) SPI_CFG_0
+#define SPI_SEL(bus) SPI_SEL_0
+#define SPI_BITS(bus) SPI_BITS_0
+#define SPI_CSS_BIT(bus) SPI_CSS_BIT_0
+#endif
+#if HAS_SPI_1
+#define SPI_BUF(bus) SPI_BUF_1
+#define SPI_CSR(bus) SPI_CSR_1
+#define SPI_BAUD(bus) SPI_BAUD_1
+#define SPI_GCR(bus) SPI_GCR_1
+#define SPI_CFG_MASK(bus) SPI_CFG_MASK_1
+#define SPI_DMA_TX(bus) SPI_DMA_TX_1
+#define SPI_DMA_RX(bus) SPI_DMA_RX_1
+#define SPI_CFG(bus) SPI_CFG_1
+#define SPI_SEL(bus) SPI_SEL_1
+#define SPI_BITS(bus) SPI_BITS_1
+#define SPI_CSS_BIT(bus) SPI_CSS_BIT_1
+#endif
+
+#endif /* MULTI_SPI */
+