+/* Default pin usage for existing Altus Metrum devices */
+#if !HAS_SPI_0 && !HAS_SPI_1
+#define HAS_SPI_0 1
+#define SPI_0_ALT_2 1
+#endif
+
+#ifndef SPI_CONST
+#define SPI_CONST 0xff
+#endif
+
+/*
+ * USART0 SPI config alt 1
+ *
+ * MO P0_3
+ * MI P0_2
+ * CLK P0_5
+ * SS P0_4
+ *
+ * USART0 SPI config alt 2
+ *
+ * MO P1_5
+ * MI P1_4
+ * CLK P1_3
+ * CSS P1_2
+ *
+ * USART1 SPI config alt 1
+ *
+ * MO P0_4
+ * MI P0_5
+ * CLK P0_3
+ * SS P0_2
+ *
+ * USART1 SPI config alt 2
+ *
+ * MO P1_6
+ * MI P1_7
+ * CLK P1_5
+ * SS P1_4
+ *
+ *
+ * Chip select is the responsibility of the caller in master mode
+ */
+
+#if HAS_SPI_0
+#define SPI_CSR U0CSR
+#define SPI_BUF U0DBUFXADDR
+#define SPI_BAUD U0BAUD
+#define SPI_GCR U0GCR
+#define SPI_CFG_MASK PERCFG_U0CFG_ALT_MASK
+#define SPI_DMA_TX DMA_CFG0_TRIGGER_UTX0
+#define SPI_DMA_RX DMA_CFG0_TRIGGER_URX0
+
+#if SPI_0_ALT_1
+#define SPI_CFG PERCFG_U0CFG_ALT_1
+#define SPI_SEL P0SEL
+#define SPI_BITS (1 << 3) | (1 << 2) | (1 << 5)
+#define SPI_CSS_BIT (1 << 4)
+#endif
+
+#if SPI_0_ALT_2
+#define SPI_CFG PERCFG_U0CFG_ALT_2
+#define SPI_SEL P1SEL
+#define SPI_PRI P2SEL_PRI3P1_USART0
+#define SPI_BITS (1 << 5) | (1 << 4) | (1 << 3)
+#define SPI_CSS_BIT (1 << 2)
+#endif
+
+#endif
+
+#if HAS_SPI_1
+#define SPI_CSR U1CSR
+#define SPI_BUF U1DBUFXADDR
+#define SPI_BAUD U1BAUD
+#define SPI_GCR U1GCR
+#define SPI_CFG_MASK PERCFG_U1CFG_ALT_MASK
+#define SPI_DMA_TX DMA_CFG0_TRIGGER_UTX1
+#define SPI_DMA_RX DMA_CFG0_TRIGGER_URX1
+
+#if SPI_1_ALT_1
+#define SPI_CFG PERCFG_U1CFG_ALT_1
+#define SPI_SEL P0SEL
+#define SPI_BITS (1 << 4) | (1 << 5) | (1 << 3)
+#define SPI_CSS_BIT (1 << 2)
+#endif
+
+#if SPI_1_ALT_2
+#define SPI_CFG PERCFG_U1CFG_ALT_2
+#define SPI_SEL P1SEL
+#define SPI_PRI P2SEL_PRI3P1_USART1
+#define SPI_BITS (1 << 6) | (1 << 7) | (1 << 5)
+#define SPI_CSS_BIT (1 << 4)
+#endif
+
+#endif
+
+#if AO_SPI_SLAVE
+#define CSS SPI_CSS_BIT
+#define UxCSR_DIRECTION UxCSR_SLAVE
+#else
+#define CSS 0
+#define UxCSR_DIRECTION UxCSR_MASTER
+#endif
+