+Layer(5 "outline")
+(
+ Attribute("PCB::skip-drc" "1")
+ Line[0 0 89000 0 1000 2000 "lock"]
+ Line[89000 0 89000 2600 1000 2000 "lock"]
+ Line[89000 2600 139000 2600 1000 2000 "lock"]
+ Line[139000 2600 139000 0 1000 2000 "lock"]
+ Line[139000 0 325000 0 1000 2000 "lock"]
+ Line[325000 0 325000 125000 1000 2000 "lock"]
+ Line[325000 125000 0 125000 1000 2000 "lock"]
+ Line[0 125000 0 0 1000 2000 "lock"]
+)
+Layer(6 "silk")