1 # STMicroelectronics STM32MP13x (Single Cortex-A7)
2 # http://www.st.com/stm32mp1
4 # HLA does not support custom CSW nor AP other than 0
6 echo "ERROR: HLA transport cannot work with this target."
7 echo "ERROR: To use STLink switch to DAP mode, as in \"board/stm32mp13x_dk.cfg\"."
11 source [find target/swj-dp.tcl]
13 if { [info exists CHIPNAME] } {
14 set _CHIPNAME $CHIPNAME
16 set _CHIPNAME stm32mp13x
19 if { [info exists CPUTAPID] } {
20 set _CPUTAPID $CPUTAPID
23 set _CPUTAPID 0x6ba00477
25 set _CPUTAPID 0x6ba02477
29 # Chip Level TAP Controller, only in jtag mode
30 if { [info exists CLCTAPID] } {
31 set _CLCTAPID $CLCTAPID
33 set _CLCTAPID 0x06501041
36 swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4
38 jtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
41 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
43 # NOTE: keep ap-num and dbgbase to speed-up examine after reset
44 # NOTE: do not change the order of target create
45 target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
46 target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
47 target create $_CHIPNAME.cpu cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
49 $_CHIPNAME.cpu cortex_a maskisr on
50 $_CHIPNAME.cpu cortex_a dacrfixup on
52 # interface does not work while srst is asserted
53 # this is target specific, valid for every board
54 # srst resets the debug unit, behavior equivalent to "srst_pulls_trst"
55 reset_config srst_gates_jtag srst_pulls_trst
58 adapter srst pulse_width 200
59 # bootrom has an internal timeout of 1 second for detecting the boot flash.
60 # wait at least 1 second to guarantee we are out of bootrom
61 adapter srst delay 1100
63 add_help_text axi_secure "Set secure mode for following AXI accesses"
65 $::_CHIPNAME.dap apsel 0
66 $::_CHIPNAME.dap apcsw 0x10006000
69 add_help_text axi_nsecure "Set non-secure mode for following AXI accesses"
71 $::_CHIPNAME.dap apsel 0
72 $::_CHIPNAME.dap apcsw 0x30006000
77 proc dbgmcu_enable_debug {} {
78 # keep clock enabled in low-power
79 ## catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000004}
80 # freeze watchdog 1 and 2 on core halted
81 catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
82 catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
85 proc toggle_cpu_dbg_claim0 {} {
86 # toggle CPU0 DBG_CLAIM[0]
87 $::_CHIPNAME.ap1 mww 0xe00d0fa0 1
88 $::_CHIPNAME.ap1 mww 0xe00d0fa4 1
91 # FIXME: most of handlers below will be removed once reset framework get merged
92 $_CHIPNAME.ap1 configure -event reset-deassert-pre {
93 adapter deassert srst deassert trst
95 catch {$::_CHIPNAME.dap apid 1}
97 $_CHIPNAME.cpu configure -event reset-deassert-pre {$::_CHIPNAME.cpu arp_examine}
98 $_CHIPNAME.cpu configure -event reset-deassert-post {toggle_cpu_dbg_claim0; dbgmcu_enable_debug}
99 $_CHIPNAME.ap1 configure -event examine-start {dap init}
100 $_CHIPNAME.ap1 configure -event examine-end {dbgmcu_enable_debug}