2 * Copyright © 2018 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
20 typedef volatile uint32_t vuint32_t;
21 typedef volatile void * vvoid_t;
22 typedef volatile uint16_t vuint16_t;
23 typedef volatile uint8_t vuint8_t;
30 extern struct stm_pwr stm_pwr;
32 #define stm_pwr (*((struct stm_pwr *) 0x40007000))
34 #define STM_PWR_CR_FISSR 21
35 #define STM_PWR_CR_FMSSR 20
36 #define STM_PWR_CR_VOS 14
37 #define STM_PWR_CR_VOS_SCALE_MODE_3 1
38 #define STM_PWR_CR_VOS_SCALE_MODE_2 2
39 #define STM_PWR_CR_VOS_SCALE_MODE_1 3
40 #define STM_PWR_CR_VOS_SCALE_MODE_MASK 3
41 #define STM_PWR_CR_ADCDC1 13
42 #define STM_PWR_CR_MRLVDS 11
43 #define STM_PWR_CR_LPLVDS 10
44 #define STM_PWR_CR_FPDS 9
45 #define STM_PWR_CR_DBP 8
46 #define STM_PWR_CR_PLS 5
47 #define STM_PWR_CR_PVDE 4
48 #define STM_PWR_CR_CSBF 3
49 #define STM_PWR_CR_CWUF 2
50 #define STM_PWR_CR_PDDS 1
51 #define STM_PWR_CR_LPDS 0
103 extern struct stm_rcc stm_rcc;
105 #define stm_rcc (*((struct stm_rcc *) 0x40023800))
107 /* Internal HSI is 16MHz */
108 #define STM_HSI_FREQ 16000000
110 #define STM_RCC_CR_PLLI2SRDY (27)
111 #define STM_RCC_CR_PLLI2SON (26)
112 #define STM_RCC_CR_PLLRDY (25)
113 #define STM_RCC_CR_PLLON (24)
114 #define STM_RCC_CR_CSSON (19)
115 #define STM_RCC_CR_HSEBYP (18)
116 #define STM_RCC_CR_HSERDY (17)
117 #define STM_RCC_CR_HSEON (16)
118 #define STM_RCC_CR_HSICAL (8)
119 #define STM_RCC_CR_HSITRIM (3)
120 #define STM_RCC_CR_HSIRDY (1)
121 #define STM_RCC_CR_HSION (0)
123 #define STM_RCC_PLLCFGR_PLLM 0
124 #define STM_RCC_PLLCFGR_PLLM_MASK 0x3f
125 #define STM_RCC_PLLCFGR_PLLN 6
126 #define STM_RCC_PLLCFGR_PLLN_MASK 0x1ff
127 #define STM_RCC_PLLCFGR_PLLP 16
128 #define STM_RCC_PLLCFGR_PLLP_DIV_2 0
129 #define STM_RCC_PLLCFGR_PLLP_DIV_4 1
130 #define STM_RCC_PLLCFGR_PLLP_DIV_6 2
131 #define STM_RCC_PLLCFGR_PLLP_DIV_8 3
132 #define STM_RCC_PLLCFGR_PLLP_MASK 0x3
133 #define STM_RCC_PLLCFGR_PLLSRC 22
134 #define STM_RCC_PLLCFGR_PLLSRC_HSI 0
135 #define STM_RCC_PLLCFGR_PLLSRC_HSE 1
136 #define STM_RCC_PLLCFGR_PLLQ 24
137 #define STM_RCC_PLLCFGR_PLLQ_MASK 0xf
138 #define STM_RCC_PLLCFGR_PLLR 28
139 #define STM_RCC_PLLCFGR_PLLR_MASK 0x7
141 #define STM_RCC_CFGR_MCO2 (30)
142 #define STM_RCC_CFGR_MCO2PRE (27)
143 #define STM_RCC_CFGR_MCO1PRE (24)
144 #define STM_RCC_CFGR_MCO1 (21)
145 #define STM_RCC_CFGR_RTCPRE (16)
147 #define STM_RCC_CFGR_PPRE2 (13)
148 #define STM_RCC_CFGR_PPRE2_DIV_1 0
149 #define STM_RCC_CFGR_PPRE2_DIV_2 4
150 #define STM_RCC_CFGR_PPRE2_DIV_4 5
151 #define STM_RCC_CFGR_PPRE2_DIV_8 6
152 #define STM_RCC_CFGR_PPRE2_DIV_16 7
153 #define STM_RCC_CFGR_PPRE2_MASK 7
155 #define STM_RCC_CFGR_PPRE1 (10)
156 #define STM_RCC_CFGR_PPRE1_DIV_1 0
157 #define STM_RCC_CFGR_PPRE1_DIV_2 4
158 #define STM_RCC_CFGR_PPRE1_DIV_4 5
159 #define STM_RCC_CFGR_PPRE1_DIV_8 6
160 #define STM_RCC_CFGR_PPRE1_DIV_16 7
161 #define STM_RCC_CFGR_PPRE1_MASK 7
163 #define STM_RCC_CFGR_HPRE (4)
164 #define STM_RCC_CFGR_HPRE_DIV_1 0x0
165 #define STM_RCC_CFGR_HPRE_DIV_2 0x8
166 #define STM_RCC_CFGR_HPRE_DIV_4 0x9
167 #define STM_RCC_CFGR_HPRE_DIV_8 0xa
168 #define STM_RCC_CFGR_HPRE_DIV_16 0xb
169 #define STM_RCC_CFGR_HPRE_DIV_64 0xc
170 #define STM_RCC_CFGR_HPRE_DIV_128 0xd
171 #define STM_RCC_CFGR_HPRE_DIV_256 0xe
172 #define STM_RCC_CFGR_HPRE_DIV_512 0xf
173 #define STM_RCC_CFGR_HPRE_MASK 0xf
175 #define STM_RCC_CFGR_SWS (2)
176 #define STM_RCC_CFGR_SWS_HSI 0
177 #define STM_RCC_CFGR_SWS_HSE 1
178 #define STM_RCC_CFGR_SWS_PLL 2
179 #define STM_RCC_CFGR_SWS_MASK 3
181 #define STM_RCC_CFGR_SW (0)
182 #define STM_RCC_CFGR_SW_HSI 0
183 #define STM_RCC_CFGR_SW_HSE 1
184 #define STM_RCC_CFGR_SW_PLL 2
185 #define STM_RCC_CFGR_SW_MASK 3
187 #define STM_RCC_AHB1ENR_IOPAEN 0
188 #define STM_RCC_AHB1ENR_IOPBEN 1
189 #define STM_RCC_AHB1ENR_IOPCEN 2
190 #define STM_RCC_AHB1ENR_IOPDEN 3
191 #define STM_RCC_AHB1ENR_IOPEEN 4
192 #define STM_RCC_AHB1ENR_IOPFEN 5
193 #define STM_RCC_AHB1ENR_IOPGEN 6
194 #define STM_RCC_AHB1ENR_IOPHEN 7
196 #define STM_RCC_APB1ENR_UART8EN 31
197 #define STM_RCC_APB1ENR_UART7EN 30
198 #define STM_RCC_APB1ENR_DACEN 29
199 #define STM_RCC_APB1ENR_PWREN 28
200 #define STM_RCC_APB1ENR_CAN3EN 27
201 #define STM_RCC_APB1ENR_CAN2EN 26
202 #define STM_RCC_APB1ENR_CAN1EN 25
203 #define STM_RCC_APB1ENR_I2CFMP1EN 24
204 #define STM_RCC_APB1ENR_I2C3EN 23
205 #define STM_RCC_APB1ENR_I2C2EN 22
206 #define STM_RCC_APB1ENR_I2C1EN 21
207 #define STM_RCC_APB1ENR_UART5EN 20
208 #define STM_RCC_APB1ENR_UART4EN 19
209 #define STM_RCC_APB1ENR_USART3EN 18
210 #define STM_RCC_APB1ENR_USART2EN 17
211 #define STM_RCC_APB1ENR_SPI3EN 15
212 #define STM_RCC_APB1ENR_SPI2EN 14
213 #define STM_RCC_APB1ENR_WWDGEN 11
214 #define STM_RCC_APB1ENR_RTCAPBEN 10
215 #define STM_RCC_APB1ENR_LPTIMER1EN 9
216 #define STM_RCC_APB1ENR_TIM14EN 8
217 #define STM_RCC_APB1ENR_TIM13EN 7
218 #define STM_RCC_APB1ENR_TIM12EN 6
219 #define STM_RCC_APB1ENR_TIM7EN 5
220 #define STM_RCC_APB1ENR_TIM6EN 4
221 #define STM_RCC_APB1ENR_TIM5EN 3
222 #define STM_RCC_APB1ENR_TIM4EN 2
223 #define STM_RCC_APB1ENR_TIM3EN 1
224 #define STM_RCC_APB1ENR_TIM2EN 0
226 #define STM_RCC_APB2ENR_DFSDM2EN 25
227 #define STM_RCC_APB2ENR_DFSDM1EN 24
228 #define STM_RCC_APB2ENR_SAI1EN 22
229 #define STM_RCC_APB2ENR_SPI5EN 20
230 #define STM_RCC_APB2ENR_TIM11EN 18
231 #define STM_RCC_APB2ENR_TIM10EN 17
232 #define STM_RCC_APB2ENR_TIM9EN 16
233 #define STM_RCC_APB2ENR_EXITEN 15
234 #define STM_RCC_APB2ENR_SYSCFGEN 14
235 #define STM_RCC_APB2ENR_SPI4EN 13
236 #define STM_RCC_APB2ENR_SPI1EN 12
237 #define STM_RCC_APB2ENR_SDIOEN 11
238 #define STM_RCC_APB2ENR_ADC1EN 8
239 #define STM_RCC_APB2ENR_UART10EN 7
240 #define STM_RCC_APB2ENR_UART9EN 5
241 #define STM_RCC_APB2ENR_USART6EN 5
242 #define STM_RCC_APB2ENR_USART1EN 4
243 #define STM_RCC_APB2ENR_TIM8EN 1
244 #define STM_RCC_APB2ENR_TIM1EN 0
246 #define STM_RCC_CSR_RMVF 24
252 extern struct stm_ictr stm_ictr;
254 #define stm_ictr (*((struct stm_ictr *) 0xe000e004))
256 #define STM_ICTR_ICTR_INTLINESNUM 0
257 #define STM_ICTR_ICTR_INTLINESNUM_MASK 0xf
260 vuint32_t iser[8]; /* 0x000 0xe000e100 Set Enable Register */
262 uint8_t _unused020[0x080 - 0x020];
264 vuint32_t icer[8]; /* 0x080 0xe000e180 Clear Enable Register */
266 uint8_t _unused0a0[0x100 - 0x0a0];
268 vuint32_t ispr[8]; /* 0x100 0xe000e200 Set Pending Register */
270 uint8_t _unused120[0x180 - 0x120];
272 vuint32_t icpr[8]; /* 0x180 0xe000e280 Clear Pending Register */
274 uint8_t _unused1a0[0x200 - 0x1a0];
276 vuint32_t iabr[8]; /* 0x200 0xe000e300 Active Bit Register */
278 uint8_t _unused220[0x300 - 0x220];
280 vuint32_t ipr[60]; /* 0x300 0xe000e400 Priority Register */
283 extern struct stm_nvic stm_nvic;
285 #define stm_nvic (*((struct stm_nvic *) 0xe000e100))
287 #define IRQ_REG(irq) ((irq) >> 5)
288 #define IRQ_BIT(irq) ((irq) & 0x1f)
289 #define IRQ_MASK(irq) (1 << IRQ_BIT(irq))
290 #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1)
293 stm_nvic_set_enable(int irq) {
294 stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq);
298 stm_nvic_clear_enable(int irq) {
299 stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq);
303 stm_nvic_enabled(int irq) {
304 return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq);
308 stm_nvic_set_pending(int irq) {
309 stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq);
313 stm_nvic_clear_pending(int irq) {
314 stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq);
318 stm_nvic_pending(int irq) {
319 return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq);
323 stm_nvic_active(int irq) {
324 return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq);
327 #define IRQ_PRIO_REG(irq) ((irq) >> 2)
328 #define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3)
329 #define IRQ_PRIO_MASK(irq) (0xff << IRQ_PRIO_BIT(irq))
332 stm_nvic_set_priority(int irq, uint8_t prio) {
333 int n = IRQ_PRIO_REG(irq);
337 v &= ~IRQ_PRIO_MASK(irq);
338 v |= (prio) << IRQ_PRIO_BIT(irq);
342 static inline uint8_t
343 stm_nvic_get_priority(int irq) {
344 return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
347 #define isr(name) void stm_ ## name ## _isr(void)
384 isr(tim_trg_com_tim11);
403 isr(tim8_trg_com_tim14);
457 #define STM_ISR_WWDG_POS 0
458 #define STM_ISR_PVD_POS 1
459 #define STM_ISR_TAMPER_STAMP_POS 2
460 #define STM_ISR_RTC_WKUP_POS 3
461 #define STM_ISR_FLASH_POS 4
462 #define STM_ISR_RCC_POS 5
463 #define STM_ISR_EXTI0_POS 6
464 #define STM_ISR_EXTI1_POS 7
465 #define STM_ISR_EXTI2_POS 8
466 #define STM_ISR_EXTI3_POS 9
467 #define STM_ISR_EXTI4_POS 10
468 #define STM_ISR_DMA1_STREAM0_POS 11
469 #define STM_ISR_DMA1_STREAM1_POS 12
470 #define STM_ISR_DMA1_STREAM2_POS 13
471 #define STM_ISR_DMA1_STREAM3_POS 14
472 #define STM_ISR_DMA1_STREAM4_POS 15
473 #define STM_ISR_DMA1_STREAM5_POS 16
474 #define STM_ISR_DMA1_STREAM6_POS 17
475 #define STM_ISR_ADC_POS 18
476 #define STM_ISR_CAN1_TX_POS 19
477 #define STM_ISR_CAN1_RX0_POS 20
478 #define STM_ISR_CAN1_RX1_POS 21
479 #define STM_ISR_CAN1_SCE_POS 22
480 #define STM_ISR_EXTI9_5_POS 23
481 #define STM_ISR_USART1_POS 37
482 #define STM_ISR_USART2_POS 38
483 #define STM_ISR_USART3_POS 39
484 #define STM_ISR_UART4_POS 52
485 #define STM_ISR_UART5_POS 53
486 #define STM_ISR_USART6_POS 71
487 #define STM_ISR_UART7_POS 82
488 #define STM_ISR_UART9_POS 88
489 #define STM_ISR_UART10_POS 89
491 #define STM_ISR_EXTI15_10_POS 40
504 extern struct stm_flash stm_flash;
506 #define stm_flash (*((struct stm_flash *) 0x40023c00))
508 #define STM_FLASH_ACR_DCRST 12
509 #define STM_FLASH_ACR_ICRST 11
510 #define STM_FLASH_ACR_DCEN 10
511 #define STM_FLASH_ACR_ICEN 9
512 #define STM_FLASH_ACR_PRFTEN 8
513 #define STM_FLASH_ACR_LATENCY 0
515 struct stm_flash_size {
519 extern struct stm_flash_size stm_flash_size;
521 #define stm_flash_size (*((struct stm_flash_size *) 0x1fff7a22))
538 #define STM_MODER_SHIFT(pin) ((pin) << 1)
539 #define STM_MODER_MASK 3
540 #define STM_MODER_INPUT 0
541 #define STM_MODER_OUTPUT 1
542 #define STM_MODER_ALTERNATE 2
543 #define STM_MODER_ANALOG 3
546 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
547 gpio->moder = ((gpio->moder &
548 ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
549 value << STM_MODER_SHIFT(pin));
552 static inline uint32_t
553 stm_moder_get(struct stm_gpio *gpio, int pin) {
554 return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
557 #define STM_OTYPER_SHIFT(pin) (pin)
558 #define STM_OTYPER_MASK 1
559 #define STM_OTYPER_PUSH_PULL 0
560 #define STM_OTYPER_OPEN_DRAIN 1
563 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
564 gpio->otyper = ((gpio->otyper &
565 ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
566 value << STM_OTYPER_SHIFT(pin));
569 static inline uint32_t
570 stm_otyper_get(struct stm_gpio *gpio, int pin) {
571 return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
574 #define STM_OSPEEDR_SHIFT(pin) ((pin) << 1)
575 #define STM_OSPEEDR_MASK 3
576 #define STM_OSPEEDR_LOW 0 /* 2-8MHz */
577 #define STM_OSPEEDR_MEDIUM 1 /* 12.5-50MHz */
578 #define STM_OSPEEDR_FAST 2 /* 25-100MHz */
579 #define STM_OSPEEDR_HIGH 3 /* 50-100MHz */
582 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
583 gpio->ospeedr = ((gpio->ospeedr &
584 ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
585 value << STM_OSPEEDR_SHIFT(pin));
588 static inline uint32_t
589 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
590 return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
593 #define STM_PUPDR_SHIFT(pin) ((pin) << 1)
594 #define STM_PUPDR_MASK 3
595 #define STM_PUPDR_NONE 0
596 #define STM_PUPDR_PULL_UP 1
597 #define STM_PUPDR_PULL_DOWN 2
598 #define STM_PUPDR_RESERVED 3
601 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
602 gpio->pupdr = ((gpio->pupdr &
603 ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
604 value << STM_PUPDR_SHIFT(pin));
607 static inline uint32_t
608 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
609 return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
612 #define STM_AFR_SHIFT(pin) ((pin) << 2)
613 #define STM_AFR_MASK 0xf
614 #define STM_AFR_NONE 0
615 #define STM_AFR_AF0 0x0
616 #define STM_AFR_AF1 0x1
617 #define STM_AFR_AF2 0x2
618 #define STM_AFR_AF3 0x3
619 #define STM_AFR_AF4 0x4
620 #define STM_AFR_AF5 0x5
621 #define STM_AFR_AF6 0x6
622 #define STM_AFR_AF7 0x7
623 #define STM_AFR_AF8 0x8
624 #define STM_AFR_AF9 0x9
625 #define STM_AFR_AF10 0xa
626 #define STM_AFR_AF11 0xb
627 #define STM_AFR_AF12 0xc
628 #define STM_AFR_AF13 0xd
629 #define STM_AFR_AF14 0xe
630 #define STM_AFR_AF15 0xf
633 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
635 * Set alternate pin mode too
637 stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
639 gpio->afrl = ((gpio->afrl &
640 ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
641 value << STM_AFR_SHIFT(pin));
644 gpio->afrh = ((gpio->afrh &
645 ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
646 value << STM_AFR_SHIFT(pin));
650 static inline uint32_t
651 stm_afr_get(struct stm_gpio *gpio, int pin) {
653 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
656 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
661 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
662 /* Use the bit set/reset register to do this atomically */
663 gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
666 static inline uint8_t
667 stm_gpio_get(struct stm_gpio *gpio, int pin) {
668 return (gpio->idr >> pin) & 1;
671 static inline uint16_t
672 stm_gpio_get_all(struct stm_gpio *gpio) {
677 * We can't define these in registers.ld or our fancy
678 * ao_enable_gpio macro will expand into a huge pile of code
679 * as the compiler won't do correct constant folding and
680 * dead-code elimination
683 extern struct stm_gpio stm_gpioa;
684 extern struct stm_gpio stm_gpiob;
685 extern struct stm_gpio stm_gpioc;
686 extern struct stm_gpio stm_gpiod;
687 extern struct stm_gpio stm_gpioe;
688 extern struct stm_gpio stm_gpiof;
689 extern struct stm_gpio stm_gpiog;
690 extern struct stm_gpio stm_gpioh;
692 #define stm_gpioa (*((struct stm_gpio *) 0x40020000))
693 #define stm_gpiob (*((struct stm_gpio *) 0x40020400))
694 #define stm_gpioc (*((struct stm_gpio *) 0x40020800))
695 #define stm_gpiod (*((struct stm_gpio *) 0x40020c00))
696 #define stm_gpioe (*((struct stm_gpio *) 0x40021000))
697 #define stm_gpiof (*((struct stm_gpio *) 0x40021400))
698 #define stm_gpiog (*((struct stm_gpio *) 0x40021800))
699 #define stm_gpioh (*((struct stm_gpio *) 0x40021c00))
747 vuint8_t pad_d90[0xf00 - 0xd90];
752 extern struct stm_scb stm_scb;
754 #define stm_scb (*((struct stm_scb *) 0xe000ed00))
756 #define STM_SCB_CPACR_CP(n) ((n) <<1)
757 #define STM_SCB_CPACR_DENIED 0
758 #define STM_SCB_CPACR_PRIVILEGED 1
759 #define STM_SCB_CPACR_RESERVED 2
760 #define STM_SCB_CPACR_FULL 3
761 #define STM_SCB_CPACR_FP0 STM_SCB_CPACR_CP(10)
762 #define STM_SCB_CPACR_FP1 STM_SCB_CPACR_CP(11)
764 #define STM_SCB_AIRCR_VECTKEY 16
765 #define STM_SCB_AIRCR_VECTKEY_KEY 0x05fa
766 #define STM_SCB_AIRCR_PRIGROUP 8
767 #define STM_SCB_AIRCR_SYSRESETREQ 2
768 #define STM_SCB_AIRCR_VECTCLRACTIVE 1
769 #define STM_SCB_AIRCR_VECTRESET 0
771 /* The SYSTICK starts at 0xe000e010 */
780 extern struct stm_systick stm_systick;
782 #define stm_systick (*((struct stm_systick *) 0xe000e010))
784 #define STM_SYSTICK_CSR_ENABLE 0
785 #define STM_SYSTICK_CSR_TICKINT 1
786 #define STM_SYSTICK_CSR_CLKSOURCE 2
787 #define STM_SYSTICK_CSR_CLKSOURCE_AHB_8 0
788 #define STM_SYSTICK_CSR_CLKSOURCE_AHB 1
789 #define STM_SYSTICK_CSR_COUNTFLAG 16
791 #define STM_SYSCFG_EXTICR_PA 0
792 #define STM_SYSCFG_EXTICR_PB 1
793 #define STM_SYSCFG_EXTICR_PC 2
794 #define STM_SYSCFG_EXTICR_PD 3
795 #define STM_SYSCFG_EXTICR_PE 4
796 #define STM_SYSCFG_EXTICR_PF 5
797 #define STM_SYSCFG_EXTICR_PG 6
798 #define STM_SYSCFG_EXTICR_PH 7
806 extern struct stm_syscfg stm_syscfg;
808 #define stm_syscfg (*((struct stm_syscfg *) 0x40013800))
810 #define STM_SYSCFG_MEMRMP_MEM_MODE 0
811 #define STM_SYSCFG_MEMRMP_MEM_MODE_MAIN_FLASH 0
812 #define STM_SYSCFG_MEMRMP_MEM_MODE_SYSTEM_FLASH 1
813 #define STM_SYSCFG_MEMRMP_MEM_MODE_SRAM 3
814 #define STM_SYSCFG_MEMRMP_MEM_MODE_MASK 3
816 #define STM_SYSCFG_PMC_ADC1DC2 0
819 stm_exticr_set(struct stm_gpio *gpio, int pin) {
820 uint8_t reg = pin >> 2;
821 uint8_t shift = (pin & 3) << 2;
825 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGEN);
827 if (gpio == &stm_gpioa)
828 val = STM_SYSCFG_EXTICR_PA;
829 else if (gpio == &stm_gpiob)
830 val = STM_SYSCFG_EXTICR_PB;
831 else if (gpio == &stm_gpioc)
832 val = STM_SYSCFG_EXTICR_PC;
833 else if (gpio == &stm_gpiod)
834 val = STM_SYSCFG_EXTICR_PD;
835 else if (gpio == &stm_gpioe)
836 val = STM_SYSCFG_EXTICR_PE;
837 else if (gpio == &stm_gpiof)
838 val = STM_SYSCFG_EXTICR_PF;
839 else if (gpio == &stm_gpiog)
840 val = STM_SYSCFG_EXTICR_PG;
841 else if (gpio == &stm_gpioh)
842 val = STM_SYSCFG_EXTICR_PH;
844 stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
857 extern struct stm_exti stm_exti;
859 #define stm_exti (*((struct stm_exti *) 0x40013c00))
862 vuint32_t sr; /* status register */
863 vuint32_t dr; /* data register */
864 vuint32_t brr; /* baud rate register */
865 vuint32_t cr1; /* control register 1 */
867 vuint32_t cr2; /* control register 2 */
868 vuint32_t cr3; /* control register 3 */
869 vuint32_t gtpr; /* guard time and prescaler */
872 extern struct stm_usart stm_usart6;
874 #define stm_usart6 (*((struct stm_usart *) 0x40011400))
876 #define STM_USART_SR_CTS (9) /* CTS flag */
877 #define STM_USART_SR_LBD (8) /* LIN break detection flag */
878 #define STM_USART_SR_TXE (7) /* Transmit data register empty */
879 #define STM_USART_SR_TC (6) /* Transmission complete */
880 #define STM_USART_SR_RXNE (5) /* Read data register not empty */
881 #define STM_USART_SR_IDLE (4) /* IDLE line detected */
882 #define STM_USART_SR_ORE (3) /* Overrun error */
883 #define STM_USART_SR_NF (2) /* Noise detected flag */
884 #define STM_USART_SR_FE (1) /* Framing error */
885 #define STM_USART_SR_PE (0) /* Parity error */
887 #define STM_USART_CR1_OVER8 (15) /* Oversampling mode */
888 #define STM_USART_CR1_UE (13) /* USART enable */
889 #define STM_USART_CR1_M (12) /* Word length */
890 #define STM_USART_CR1_WAKE (11) /* Wakeup method */
891 #define STM_USART_CR1_PCE (10) /* Parity control enable */
892 #define STM_USART_CR1_PS (9) /* Parity selection */
893 #define STM_USART_CR1_PEIE (8) /* PE interrupt enable */
894 #define STM_USART_CR1_TXEIE (7) /* TXE interrupt enable */
895 #define STM_USART_CR1_TCIE (6) /* Transmission complete interrupt enable */
896 #define STM_USART_CR1_RXNEIE (5) /* RXNE interrupt enable */
897 #define STM_USART_CR1_IDLEIE (4) /* IDLE interrupt enable */
898 #define STM_USART_CR1_TE (3) /* Transmitter enable */
899 #define STM_USART_CR1_RE (2) /* Receiver enable */
900 #define STM_USART_CR1_RWU (1) /* Receiver wakeup */
901 #define STM_USART_CR1_SBK (0) /* Send break */
903 #define STM_USART_CR2_LINEN (14) /* LIN mode enable */
904 #define STM_USART_CR2_STOP (12) /* STOP bits */
905 #define STM_USART_CR2_STOP_MASK 3
906 #define STM_USART_CR2_STOP_1 0
907 #define STM_USART_CR2_STOP_0_5 1
908 #define STM_USART_CR2_STOP_2 2
909 #define STM_USART_CR2_STOP_1_5 3
911 #define STM_USART_CR2_CLKEN (11) /* Clock enable */
912 #define STM_USART_CR2_CPOL (10) /* Clock polarity */
913 #define STM_USART_CR2_CPHA (9) /* Clock phase */
914 #define STM_USART_CR2_LBCL (8) /* Last bit clock pulse */
915 #define STM_USART_CR2_LBDIE (6) /* LIN break detection interrupt enable */
916 #define STM_USART_CR2_LBDL (5) /* lin break detection length */
917 #define STM_USART_CR2_ADD (0)
918 #define STM_USART_CR2_ADD_MASK 0xf
920 #define STM_USART_CR3_ONEBIT (11) /* One sample bit method enable */
921 #define STM_USART_CR3_CTSIE (10) /* CTS interrupt enable */
922 #define STM_USART_CR3_CTSE (9) /* CTS enable */
923 #define STM_USART_CR3_RTSE (8) /* RTS enable */
924 #define STM_USART_CR3_DMAT (7) /* DMA enable transmitter */
925 #define STM_USART_CR3_DMAR (6) /* DMA enable receiver */
926 #define STM_USART_CR3_SCEN (5) /* Smartcard mode enable */
927 #define STM_USART_CR3_NACK (4) /* Smartcard NACK enable */
928 #define STM_USART_CR3_HDSEL (3) /* Half-duplex selection */
929 #define STM_USART_CR3_IRLP (2) /* IrDA low-power */
930 #define STM_USART_CR3_IREN (1) /* IrDA mode enable */
931 #define STM_USART_CR3_EIE (0) /* Error interrupt enable */
935 Delay after an RCC peripheral clock enabling
939 A delay between an RCC peripheral clock enable and the effective
940 peripheral enabling should be taken into account in order to manage
941 the peripheral read/write to registers.
943 This delay depends on the peripheral’s mapping:
945 • If the peripheral is mapped on AHB: the delay should be equal to
948 • If the peripheral is mapped on APB: the delay should be equal to
949 1 + (AHB/APB prescaler) cycles.
953 1. Use the DSB instruction to stall the Cortex-M4 CPU pipeline
954 until the instruction is completed.
956 2. Insert “n” NOPs between the RCC enable bit write and the
957 peripheral register writes
961 stm32f4_set_rcc(uint32_t *rcc, uint32_t value)
969 In some specific cases, DMA2 data corruption occurs when managing
970 AHB and APB2 peripherals in a concurrent way
974 When the DMA2 is managing concurrent requests of AHB and APB2
975 peripherals, the transfer on the AHB could be performed several
978 Impacted peripheral are:
980 • Quad-SPI: indirect mode read and write transfers
982 • FSMC: read and write operation with external device having FIFO
984 • GPIO: DMA2 transfers to GPIO registers (in memory-to-peripheral
985 transfer mode).The transfers from GPIOs register are not
989 The data corruption is due to multiple DMA2 accesses over AHB
990 peripheral port impacting peripherals embedding a FIFO.
992 For transfer to the internal SRAM through the DMA2 AHB peripheral
993 port the accesses could be performed several times but without data
994 corruptions in cases of concurrent requests.
998 • The DMA2 AHB memory port must be used when reading/writing
999 from/to Quad-SPI and FSMC instead of DMA2 AHB default peripheral
1002 • The DMA2 AHB memory port must be used when writing to GPIOs
1003 instead of DMA2 AHB default peripheral port.
1005 Refer to application note AN4031 section “Take benefits of DMA2
1006 controller and system architecture flexibility” for more details
1007 about DMA controller feature.
1013 #endif /* _STM32F4_H_ */