2 * Copyright © 2009 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 static volatile __data uint16_t ao_tick_count;
22 uint16_t ao_time(void) __critical
27 static __xdata uint8_t ao_forever;
30 ao_delay(uint16_t ticks)
33 ao_sleep(&ao_forever);
36 #define T1_CLOCK_DIVISOR 8 /* 24e6/8 = 3e6 */
37 #define T1_SAMPLE_TIME 30000 /* 3e6/30000 = 100 */
40 volatile __data uint8_t ao_adc_interval = 1;
41 volatile __data uint8_t ao_adc_count;
48 ISR(TIMER1_COMPA_vect)
50 void ao_timer_isr(void) __interrupt(9)
55 if (++ao_adc_count == ao_adc_interval) {
64 ao_timer_set_adc_interval(uint8_t interval) __critical
66 ao_adc_interval = interval;
75 TCCR1A = ((0 << WGM11) | /* CTC mode, OCR1A */
76 (0 << WGM10)); /* CTC mode, OCR1A */
77 TCCR1B = ((0 << ICNC1) | /* no input capture noise canceler */
78 (0 << ICES1) | /* input capture on falling edge (don't care) */
79 (0 << WGM13) | /* CTC mode, OCR1A */
80 (1 << WGM12) | /* CTC mode, OCR1A */
81 (3 << CS10)); /* clk/64 from prescaler */
84 OCR1A = 2500; /* 16MHz clock */
86 OCR1A = 1250; /* 8MHz clock */
89 TIMSK1 = (1 << OCIE1A); /* Interrupt on compare match */
91 /* NOTE: This uses a timer only present on cc1111 architecture. */
96 /* set the sample rate */
97 T1CC0H = T1_SAMPLE_TIME >> 8;
98 T1CC0L = (uint8_t) T1_SAMPLE_TIME;
100 T1CCTL0 = T1CCTL_MODE_COMPARE;
104 /* clear timer value */
107 /* enable overflow interrupt */
109 /* enable timer 1 interrupt */
112 /* enable timer 1 in module mode, dividing by 8 */
113 T1CTL = T1CTL_MODE_MODULO | T1CTL_DIV_8;
118 * AltOS always cranks the clock to the max frequency
124 /* disable RC clock */
125 CLKSEL0 &= ~(1 << RCE);
128 PLLCSR &= ~(1 << PLLE);
130 /* Enable external clock */
131 CLKSEL0 |= (1 << EXTE);
133 /* wait for external clock to be ready */
134 while ((CLKSTA & (1 << EXTON)) == 0)
137 /* select external clock */
138 CLKSEL0 |= (1 << CLKS);
140 /* Disable the clock prescaler */
142 CLKPR = (1 << CLKPCE);
144 /* Always run the system clock at 8MHz */
145 #if AVR_CLOCK > 12000000UL
152 /* Set up the PLL to use the crystal */
154 /* Use primary system clock as PLL source */
155 PLLFRQ = ((0 << PINMUX) | /* Use primary clock */
156 (0 << PLLUSB) | /* No divide by 2 for USB */
157 (0 << PLLTM0) | /* Disable high speed timer */
158 (0x4 << PDIV0)); /* 48MHz PLL clock */
160 /* Set the frequency of the crystal */
161 #if AVR_CLOCK > 12000000UL
162 PLLCSR |= (1 << PINDIV); /* For 16MHz crystal on Teensy board */
164 PLLCSR &= ~(1 << PINDIV); /* For 8MHz crystal on TeleScience board */
168 PLLCSR |= (1 << PLLE);
169 while (!(PLLCSR & (1 << PLOCK)))
172 set_sleep_mode(SLEEP_MODE_IDLE);
175 /* Switch system clock to crystal oscilator */
176 CLKCON = (CLKCON & ~CLKCON_OSC_MASK) | (CLKCON_OSC_XTAL);
178 while (!(SLEEP & SLEEP_XOSC_STB))
181 /* Crank up the timer tick and system clock speed */
182 CLKCON = ((CLKCON & ~(CLKCON_TICKSPD_MASK | CLKCON_CLKSPD_MASK)) |
183 (CLKCON_TICKSPD_1 | CLKCON_CLKSPD_1));
185 while ((CLKCON & (CLKCON_TICKSPD_MASK|CLKCON_CLKSPD_MASK)) !=
186 (CLKCON_TICKSPD_1 | CLKCON_CLKSPD_1))