2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
22 #define HAS_TASK_QUEUE 1
24 /* 8MHz High speed external crystal */
25 #define AO_HSE 8000000
27 /* PLLVCO = 96MHz (so that USB will work) */
29 #define AO_RCC_CFGR_PLLMUL (STM_RCC_CFGR_PLLMUL_12)
31 /* SYSCLK = 32MHz (no need to go faster than CPU) */
33 #define AO_RCC_CFGR_PLLDIV (STM_RCC_CFGR_PLLDIV_3)
35 /* HCLK = 32MHz (CPU clock) */
36 #define AO_AHB_PRESCALER 1
37 #define AO_RCC_CFGR_HPRE_DIV STM_RCC_CFGR_HPRE_DIV_1
39 /* Run APB1 at 16MHz (HCLK/2) */
40 #define AO_APB1_PRESCALER 2
41 #define AO_RCC_CFGR_PPRE1_DIV STM_RCC_CFGR_PPRE2_DIV_2
43 /* Run APB2 at 16MHz (HCLK/2) */
44 #define AO_APB2_PRESCALER 2
45 #define AO_RCC_CFGR_PPRE2_DIV STM_RCC_CFGR_PPRE2_DIV_2
47 #define HAS_SERIAL_1 0
48 #define USE_SERIAL_1_STDIN 0
49 #define SERIAL_1_PB6_PB7 0
50 #define SERIAL_1_PA9_PA10 1
52 #define HAS_SERIAL_2 0
53 #define USE_SERIAL_2_STDIN 0
54 #define SERIAL_2_PA2_PA3 0
55 #define SERIAL_2_PD5_PD6 0
57 #define HAS_SERIAL_3 0
58 #define USE_SERIAL_3_STDIN 0
59 #define SERIAL_3_PB10_PB11 0
60 #define SERIAL_3_PC10_PC11 1
61 #define SERIAL_3_PD8_PD9 0
64 #define USE_INTERNAL_FLASH 0
68 #define HAS_TELEMETRY 0
69 #define PACKET_HAS_SLAVE 0
72 #define HAS_SPI_SLAVE_1 1
73 #define SPI_1_PA5_PA6_PA7 1
74 #define SPI_1_PB3_PB4_PB5 0
75 #define SPI_1_PE13_PE14_PE15 0
76 #define SPI_1_OSPEEDR STM_OSPEEDR_10MHz
79 #define SPI_2_PB13_PB14_PB15 1
80 #define SPI_2_PD1_PD3_PD4 0
81 #define SPI_2_OSPEEDR STM_OSPEEDR_10MHz
83 #define SPI_2_PORT (&stm_gpiob)
84 #define SPI_2_SCK_PIN 13
85 #define SPI_2_MISO_PIN 14
86 #define SPI_2_MOSI_PIN 15
87 #define SPI_SLAVE_INDEX 1
90 #define I2C_1_PB8_PB9 0
93 #define I2C_2_PB10_PB11 0
95 #define LOW_LEVEL_DEBUG 0
97 #define LED_PORT_0_ENABLE STM_RCC_AHBENR_GPIOAEN
99 #define LED_PORT_0 (&stm_gpioa)
100 #define LED_PORT_0_MASK (0xff)
101 #define LED_PORT_0_SHIFT 0
102 #define LED_PIN_RED 8
103 #define LED_PIN_GREEN 9
104 #define AO_LED_RED (1 << LED_PIN_RED)
105 #define AO_LED_GREEN (1 << LED_PIN_GREEN)
107 #define LEDS_AVAILABLE (AO_LED_RED | AO_LED_GREEN)
112 #define HAS_ADC_TEMP 1
119 #define M25_MAX_CHIPS 1
120 #define AO_M25_SPI_CS_PORT (&stm_gpioa)
121 #define AO_M25_SPI_CS_MASK (1 << 3)
122 #define AO_M25_SPI_BUS AO_SPI_2_PB13_PB14_PB15
128 #define AO_DATA_RING 32
132 int16_t adc[AO_ADC_NUM];
135 #define AO_ADC_TEMP 16
137 #define AO_ADC_RCC_AHBENR 0
139 #define AO_NUM_ADC_PIN 0
143 #define AO_ADC_SQ1 AO_ADC_TEMP
146 #endif /* _AO_PINS_H_ */