2 * Copyright © 2010 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
22 #define HAS_RADIO_RATE 1
23 #define HAS_TELEMETRY 0
29 #define HAS_SERIAL_1 0
35 #define USE_INTERNAL_FLASH 1
36 #define IGNITE_ON_P0 0
37 #define PACKET_HAS_MASTER 0
38 #define PACKET_HAS_SLAVE 0
39 #define AO_DATA_RING 32
40 #define HAS_FIXED_PAD_BOX 1
42 /* 8MHz High speed external crystal */
43 #define AO_HSE 8000000
45 /* PLLVCO = 96MHz (so that USB will work) */
47 #define AO_RCC_CFGR_PLLMUL (STM_RCC_CFGR_PLLMUL_12)
49 #define AO_CC1200_FOSC 40000000
51 /* SYSCLK = 32MHz (no need to go faster than CPU) */
53 #define AO_RCC_CFGR_PLLDIV (STM_RCC_CFGR_PLLDIV_3)
55 /* HCLK = 32MHz (CPU clock) */
56 #define AO_AHB_PRESCALER 1
57 #define AO_RCC_CFGR_HPRE_DIV STM_RCC_CFGR_HPRE_DIV_1
59 /* Run APB1 at 16MHz (HCLK/2) */
60 #define AO_APB1_PRESCALER 2
61 #define AO_RCC_CFGR_PPRE1_DIV STM_RCC_CFGR_PPRE2_DIV_2
63 /* Run APB2 at 16MHz (HCLK/2) */
64 #define AO_APB2_PRESCALER 2
65 #define AO_RCC_CFGR_PPRE2_DIV STM_RCC_CFGR_PPRE2_DIV_2
68 #define USE_INTERNAL_FLASH 1
69 #define USE_EEPROM_CONFIG 1
70 #define USE_STORAGE_CONFIG 0
74 #define HAS_RADIO_RATE 1
75 #define HAS_TELEMETRY 0
79 #define SPI_1_PA5_PA6_PA7 0
80 #define SPI_1_PB3_PB4_PB5 0
81 #define SPI_1_PE13_PE14_PE15 0
83 #define HAS_SPI_2 1 /* CC1200 */
84 #define SPI_2_PB13_PB14_PB15 1
85 #define SPI_2_PD1_PD3_PD4 0
86 #define SPI_2_GPIO (&stm_gpiob)
90 #define SPI_2_OSPEEDR STM_OSPEEDR_10MHz
96 #define PACKET_HAS_SLAVE 0
97 #define PACKET_HAS_MASTER 0
99 #define FAST_TIMER_FREQ 10000 /* .1ms for debouncing */
102 * Radio is a cc1200 connected via SPI
105 #define AO_RADIO_CAL_DEFAULT 5695733
107 #define AO_FEC_DEBUG 0
108 #define AO_CC1200_SPI_CS_PORT (&stm_gpioa)
109 #define AO_CC1200_SPI_CS_PIN 7
110 #define AO_CC1200_SPI_BUS AO_SPI_2_PB13_PB14_PB15
111 #define AO_CC1200_SPI stm_spi2
113 #define AO_CC1200_INT_PORT (&stm_gpiob)
114 #define AO_CC1200_INT_PIN (11)
116 #define AO_CC1200_INT_GPIO 2
117 #define AO_CC1200_INT_GPIO_IOCFG CC1200_IOCFG2
119 #define LED_PORT_0 (&stm_gpioa)
120 #define LED_PORT_1 (&stm_gpiob)
122 #define LED_PORT_0_ENABLE STM_RCC_AHBENR_GPIOAEN
123 #define LED_PORT_1_ENABLE STM_RCC_AHBENR_GPIOBEN
125 /* Port A, pins 4-6 */
126 #define LED_PORT_0_SHIFT 4
127 #define LED_PORT_0_MASK 0x7
128 #define LED_PIN_GREEN 0
129 #define LED_PIN_AMBER 1
130 #define LED_PIN_RED 2
131 #define AO_LED_RED (1 << LED_PIN_RED)
132 #define AO_LED_AMBER (1 << LED_PIN_AMBER)
133 #define AO_LED_GREEN (1 << LED_PIN_GREEN)
135 /* Port B, pins 3-5 */
136 #define LED_PORT_1_SHIFT 0
137 #define LED_PORT_1_MASK (0x7 << 3)
138 #define LED_PIN_CONT_1 3
139 #define LED_PIN_CONT_0 4
140 #define LED_PIN_ARMED 5
142 #define AO_LED_ARMED (1 << LED_PIN_ARMED)
143 #define AO_LED_CONTINUITY(c) (1 << (4 - (c)))
144 #define AO_LED_CONTINUITY_MASK (0x3 << 3)
146 #define LEDS_AVAILABLE (LED_PORT_0_MASK|LED_PORT_1_MASK)
148 #define SPI_CS_PORT P1
149 #define SPI_CS_SEL P1SEL
150 #define SPI_CS_DIR P1DIR
152 #define SPI_CONST 0x00
155 #define AO_PAD_PORT (&stm_gpiob)
157 #define AO_PAD_PIN_0 9
158 #define AO_PAD_ADC_0 0
160 #define AO_PAD_PIN_1 8
161 #define AO_PAD_ADC_1 1
163 #define AO_PAD_ALL_PINS ((1 << AO_PAD_PIN_0) | (1 << AO_PAD_PIN_1))
164 #define AO_PAD_ALL_CHANNELS ((1 << 0) | (1 << 1))
166 /* test these values with real igniters */
167 #define AO_PAD_RELAY_CLOSED 3524
168 #define AO_PAD_NO_IGNITER 16904
169 #define AO_PAD_GOOD_IGNITER 22514
171 #define AO_PAD_ADC_PYRO 8
172 #define AO_PAD_ADC_BATT 2
174 #define AO_ADC_FIRST_PIN 0
178 #define AO_ADC_SQ1 AO_PAD_ADC_0
179 #define AO_ADC_SQ2 AO_PAD_ADC_1
180 #define AO_ADC_SQ3 AO_PAD_ADC_PYRO
181 #define AO_ADC_SQ4 AO_PAD_ADC_BATT
183 #define AO_PYRO_R_PYRO_SENSE 200
184 #define AO_PYRO_R_SENSE_GND 22
186 #define AO_FIRE_R_POWER_FET 0
187 #define AO_FIRE_R_FET_SENSE 200
188 #define AO_FIRE_R_SENSE_GND 22
190 #define HAS_ADC_TEMP 0
193 int16_t sense[AO_PAD_NUM];
198 #define AO_ADC_DUMP(p) \
199 printf ("tick: %5u 0: %5d 1: %5d pyro: %5d batt %5d\n", \
206 #define AO_ADC_PINS ((1 << AO_PAD_ADC_0) | \
207 (1 << AO_PAD_ADC_1) | \
208 (1 << AO_PAD_ADC_PYRO) | \
209 (1 << AO_PAD_ADC_BATT))
211 #endif /* _AO_PINS_H_ */