2 * Copyright © 2010 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
23 #define HAS_RADIO_RATE 1
24 #define HAS_TELEMETRY 0
29 #define BEEPER_CHANNEL 4
30 #define BEEPER_TIMER 3
32 #define HAS_SERIAL_1 0
38 #define USE_INTERNAL_FLASH 0
39 #define IGNITE_ON_P0 0
40 #define PACKET_HAS_MASTER 0
41 #define PACKET_HAS_SLAVE 0
42 #define AO_DATA_RING 32
43 #define HAS_FIXED_PAD_BOX 1
45 #define AO_LOG_FORMAT AO_LOG_FORMAT_TELEFIRETWO
47 #define LOG_ERASE_MARK 0x55
49 /* 8MHz High speed external crystal */
50 #define AO_HSE 8000000
52 /* PLLVCO = 96MHz (so that USB will work) */
54 #define AO_RCC_CFGR_PLLMUL (STM_RCC_CFGR_PLLMUL_12)
56 #define AO_CC1200_FOSC 40000000
58 /* SYSCLK = 32MHz (no need to go faster than CPU) */
60 #define AO_RCC_CFGR_PLLDIV (STM_RCC_CFGR_PLLDIV_3)
62 /* HCLK = 32MHz (CPU clock) */
63 #define AO_AHB_PRESCALER 1
64 #define AO_RCC_CFGR_HPRE_DIV STM_RCC_CFGR_HPRE_DIV_1
66 /* Run APB1 at 16MHz (HCLK/2) */
67 #define AO_APB1_PRESCALER 2
68 #define AO_RCC_CFGR_PPRE1_DIV STM_RCC_CFGR_PPRE2_DIV_2
70 /* Run APB2 at 16MHz (HCLK/2) */
71 #define AO_APB2_PRESCALER 2
72 #define AO_RCC_CFGR_PPRE2_DIV STM_RCC_CFGR_PPRE2_DIV_2
75 #define USE_EEPROM_CONFIG 1
76 #define USE_STORAGE_CONFIG 0
79 #define HAS_RADIO_RATE 1
80 #define HAS_TELEMETRY 0
84 #define SPI_1_PA5_PA6_PA7 0
85 #define SPI_1_PB3_PB4_PB5 0
86 #define SPI_1_PE13_PE14_PE15 0
88 #define HAS_SPI_2 1 /* CC1200 */
89 #define SPI_2_PB13_PB14_PB15 1
90 #define SPI_2_PD1_PD3_PD4 0
91 #define SPI_2_GPIO (&stm_gpiob)
95 #define SPI_2_OSPEEDR STM_OSPEEDR_10MHz
101 #define PACKET_HAS_SLAVE 0
102 #define PACKET_HAS_MASTER 0
104 #define FAST_TIMER_FREQ 10000 /* .1ms for debouncing */
110 #define M25_MAX_CHIPS 1
111 #define AO_M25_SPI_CS_PORT (&stm_gpioa)
112 #define AO_M25_SPI_CS_MASK (1 << 15)
113 #define AO_M25_SPI_BUS AO_SPI_2_PB13_PB14_PB15
116 * Radio is a cc1200 connected via SPI
119 #define AO_RADIO_CAL_DEFAULT 5695733
121 #define AO_FEC_DEBUG 0
122 #define AO_CC1200_SPI_CS_PORT (&stm_gpioa)
123 #define AO_CC1200_SPI_CS_PIN 7
124 #define AO_CC1200_SPI_BUS AO_SPI_2_PB13_PB14_PB15
125 #define AO_CC1200_SPI stm_spi2
127 #define AO_CC1200_INT_PORT (&stm_gpiob)
128 #define AO_CC1200_INT_PIN (11)
130 #define AO_CC1200_INT_GPIO 2
131 #define AO_CC1200_INT_GPIO_IOCFG CC1200_IOCFG2
133 #define LED_PORT_0 (&stm_gpioa)
134 #define LED_PORT_1 (&stm_gpiob)
136 #define LED_PORT_0_ENABLE STM_RCC_AHBENR_GPIOAEN
137 #define LED_PORT_1_ENABLE STM_RCC_AHBENR_GPIOBEN
139 /* Port A, pins 4-6 */
140 #define LED_PORT_0_SHIFT 4
141 #define LED_PORT_0_MASK 0x7
142 #define LED_PIN_GREEN 0
143 #define LED_PIN_AMBER 1
144 #define LED_PIN_RED 2
145 #define AO_LED_RED (1 << LED_PIN_RED)
146 #define AO_LED_AMBER (1 << LED_PIN_AMBER)
147 #define AO_LED_GREEN (1 << LED_PIN_GREEN)
149 /* Port B, pins 4-5 */
150 #define LED_PORT_1_SHIFT 0
151 #define LED_PORT_1_MASK (0x3 << 4)
152 #define LED_PIN_CONT_0 4
153 #define LED_PIN_ARMED 5
155 #define AO_LED_ARMED (1 << LED_PIN_ARMED)
156 #define AO_LED_CONTINUITY(c) ((AO_LED_TYPE) (1 << (4 - (c))))
157 #define AO_LED_CONTINUITY_MASK (0x1 << 4)
159 #define LEDS_AVAILABLE (LED_PORT_0_MASK|LED_PORT_1_MASK)
163 #define AO_SIREN_PORT (&stm_gpiob)
164 #define AO_SIREN_PIN 8
168 #define AO_STROBE_PORT (&stm_gpiob)
169 #define AO_STROBE_PIN 9
171 #define SPI_CONST 0x00
174 #define AO_PAD_PORT (&stm_gpioa)
176 #define AO_PAD_PIN_0 1
177 #define AO_PAD_ADC_0 0
179 #define AO_PAD_ALL_PINS ((1 << AO_PAD_PIN_0))
180 #define AO_PAD_ALL_CHANNELS ((1 << 0))
182 /* test these values with real igniters */
183 #define AO_PAD_RELAY_CLOSED 3524
184 #define AO_PAD_NO_IGNITER 16904
185 #define AO_PAD_GOOD_IGNITER 22514
187 #define AO_PAD_ADC_PYRO 2
188 #define AO_PAD_ADC_BATT 8
190 #define AO_PAD_ADC_THRUST 3
191 #define AO_PAD_ADC_PRESSURE 18
193 #define AO_ADC_FIRST_PIN 0
195 #define AO_ADC_REFERENCE_DV 33
199 #define AO_ADC_SQ1 AO_PAD_ADC_0
200 #define AO_ADC_SQ2 AO_PAD_ADC_PYRO
201 #define AO_ADC_SQ3 AO_PAD_ADC_BATT
202 #define AO_ADC_SQ4 AO_PAD_ADC_THRUST
203 #define AO_ADC_SQ5 AO_PAD_ADC_PRESSURE
205 #define AO_PAD_R_V_BATT_BATT_SENSE 200
206 #define AO_PAD_R_BATT_SENSE_GND 22
208 #define AO_PAD_R_V_BATT_V_PYRO 200
209 #define AO_PAD_R_V_PYRO_PYRO_SENSE 200
210 #define AO_PAD_R_PYRO_SENSE_GND 22
212 #undef AO_PAD_R_V_PYRO_IGNITER
213 #define AO_PAD_R_IGNITER_IGNITER_SENSE 200
214 #define AO_PAD_R_IGNITER_SENSE_GND 22
216 #define AO_PYRO_R_PYRO_SENSE 200
217 #define AO_PYRO_R_SENSE_GND 22
219 #define AO_FIRE_R_POWER_FET 0
220 #define AO_FIRE_R_FET_SENSE 200
221 #define AO_FIRE_R_SENSE_GND 22
223 #define HAS_ADC_TEMP 0
226 int16_t sense[AO_PAD_NUM];
233 #define AO_ADC_DUMP(p) \
234 printf ("tick: %5lu 0: %5d pyro: %5d batt %5d thrust %5d pressure %5d\n", \
242 #define AO_ADC_PINS ((1 << AO_PAD_ADC_0) | \
243 (1 << AO_PAD_ADC_PYRO) | \
244 (1 << AO_PAD_ADC_BATT) | \
245 (1 << AO_PAD_ADC_THRUST) | \
246 (1 << AO_PAD_ADC_PRESSURE))
248 #endif /* _AO_PINS_H_ */