2 * Copyright © 2019 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
23 #define HAS_RADIO_RATE 1
24 #define HAS_TELEMETRY 0
29 #define HAS_SERIAL_1 0
35 #define USE_INTERNAL_FLASH 1
36 #define AO_DATA_RING 32
37 #define USE_EEPROM_CONFIG 1
38 #define USE_STORAGE_CONFIG 0
41 /* 8MHz High speed external crystal */
42 #define AO_HSE 8000000
44 /* PLLVCO = 96MHz (so that USB will work) */
46 #define AO_RCC_CFGR_PLLMUL (STM_RCC_CFGR_PLLMUL_12)
48 #define AO_CC1200_FOSC 40000000
50 /* SYSCLK = 32MHz (no need to go faster than CPU) */
52 #define AO_RCC_CFGR_PLLDIV (STM_RCC_CFGR_PLLDIV_3)
54 /* HCLK = 32MHz (CPU clock) */
55 #define AO_AHB_PRESCALER 1
56 #define AO_RCC_CFGR_HPRE_DIV STM_RCC_CFGR_HPRE_DIV_1
58 /* Run APB1 at 16MHz (HCLK/2) */
59 #define AO_APB1_PRESCALER 2
60 #define AO_RCC_CFGR_PPRE1_DIV STM_RCC_CFGR_PPRE2_DIV_2
62 /* Run APB2 at 16MHz (HCLK/2) */
63 #define AO_APB2_PRESCALER 2
64 #define AO_RCC_CFGR_PPRE2_DIV STM_RCC_CFGR_PPRE2_DIV_2
67 #define SPI_1_PA5_PA6_PA7 0
68 #define SPI_1_PB3_PB4_PB5 0
69 #define SPI_1_PE13_PE14_PE15 1
70 #define SPI_1_GPIO (&stm_gpioe)
71 #define SPI_1_OSPEEDR STM_OSPEEDR_10MHz
74 #define SPI_2_PB13_PB14_PB15 0
75 #define SPI_2_PD1_PD3_PD4 0
82 * Radio is a cc1200 connected via SPI
85 #define AO_RADIO_CAL_DEFAULT 5695733
87 #define AO_CC1200_SPI_CS_PORT (&stm_gpioe)
88 #define AO_CC1200_SPI_CS_PIN 11
89 #define AO_CC1200_SPI_BUS AO_SPI_1_PE13_PE14_PE15
90 #define AO_CC1200_SPI stm_spi1
92 #define AO_CC1200_INT_PORT (&stm_gpioe)
93 #define AO_CC1200_INT_PIN (12)
95 #define AO_CC1200_INT_GPIO 2
96 #define AO_CC1200_INT_GPIO_IOCFG CC1200_IOCFG2
99 #define LED_TYPE uint16_t
101 /* Continuity leds 1-8 */
102 #define LED_0_PORT (&stm_gpiob)
104 #define LED_1_PORT (&stm_gpiob)
106 #define LED_2_PORT (&stm_gpiob)
108 #define LED_3_PORT (&stm_gpiob)
110 #define LED_4_PORT (&stm_gpioc)
112 #define LED_5_PORT (&stm_gpioa)
114 #define LED_6_PORT (&stm_gpioa)
116 #define LED_7_PORT (&stm_gpioa)
119 #define AO_LED_CONTINUITY(c) (1 << (c))
120 #define AO_LED_CONTINUITY_MASK (0xff)
123 #define LED_8_PORT (&stm_gpioe)
126 #define AO_LED_ARMED AO_LED_8
128 /* RF good/marginal/poor */
129 #define LED_9_PORT (&stm_gpioe)
131 #define LED_10_PORT (&stm_gpioe)
133 #define LED_11_PORT (&stm_gpioe)
136 #define AO_LED_GREEN AO_LED_9
137 #define AO_LED_AMBER AO_LED_10
138 #define AO_LED_RED AO_LED_11
142 #define AO_SIREN_PORT (&stm_gpiod)
143 #define AO_SIREN_PIN 10
147 #define AO_STROBE_PORT (&stm_gpiod)
148 #define AO_STROBE_PIN 11
150 /* Pad selector is on PD0-7 */
152 #define HAS_FIXED_PAD_BOX 1
153 #define AO_PAD_SELECTOR_PORT (&stm_gpiod)
154 #define AO_PAD_SELECTOR_PINS (0xff)
156 #define SPI_CONST 0x00
159 #define AO_PAD_PORT_0 (&stm_gpiod)
160 #define AO_PAD_PORT_1 (&stm_gpiob)
162 #define AO_PAD_PIN_0 9
163 #define AO_PAD_0_PORT (&stm_gpiod)
164 #define AO_ADC_SENSE_PAD_0 3
165 #define AO_ADC_SENSE_PAD_0_PORT (&stm_gpioa)
166 #define AO_ADC_SENSE_PAD_0_PIN 3
168 #define AO_PAD_PIN_1 8
169 #define AO_PAD_1_PORT (&stm_gpiod)
170 #define AO_ADC_SENSE_PAD_1 2
171 #define AO_ADC_SENSE_PAD_1_PORT (&stm_gpioa)
172 #define AO_ADC_SENSE_PAD_1_PIN 2
174 #define AO_PAD_PIN_2 15
175 #define AO_PAD_2_PORT (&stm_gpiob)
176 #define AO_ADC_SENSE_PAD_2 1
177 #define AO_ADC_SENSE_PAD_2_PORT (&stm_gpioa)
178 #define AO_ADC_SENSE_PAD_2_PIN 1
180 #define AO_PAD_PIN_3 14
181 #define AO_PAD_3_PORT (&stm_gpiob)
182 #define AO_ADC_SENSE_PAD_3 0
183 #define AO_ADC_SENSE_PAD_3_PORT (&stm_gpioa)
184 #define AO_ADC_SENSE_PAD_3_PIN 0
186 #define AO_PAD_PIN_4 12
187 #define AO_PAD_4_PORT (&stm_gpiod)
188 #define AO_ADC_SENSE_PAD_4 7
189 #define AO_ADC_SENSE_PAD_4_PORT (&stm_gpioa)
190 #define AO_ADC_SENSE_PAD_4_PIN 7
192 #define AO_PAD_PIN_5 13
193 #define AO_PAD_5_PORT (&stm_gpiod)
194 #define AO_ADC_SENSE_PAD_5 6
195 #define AO_ADC_SENSE_PAD_5_PORT (&stm_gpioa)
196 #define AO_ADC_SENSE_PAD_5_PIN 6
198 #define AO_PAD_PIN_6 14
199 #define AO_PAD_6_PORT (&stm_gpiod)
200 #define AO_ADC_SENSE_PAD_6 5
201 #define AO_ADC_SENSE_PAD_6_PORT (&stm_gpioa)
202 #define AO_ADC_SENSE_PAD_6_PIN 5
204 #define AO_PAD_PIN_7 15
205 #define AO_PAD_7_PORT (&stm_gpiod)
206 #define AO_ADC_SENSE_PAD_7 4
207 #define AO_ADC_SENSE_PAD_7_PORT (&stm_gpioa)
208 #define AO_ADC_SENSE_PAD_7_PIN 4
210 #define AO_ADC_PYRO 8
211 #define AO_ADC_PYRO_PORT (&stm_gpiob)
212 #define AO_ADC_PYRO_PIN 0
214 #define AO_ADC_BATT 15
215 #define AO_ADC_BATT_PORT (&stm_gpioc)
216 #define AO_ADC_BATT_PIN 5
218 #define AO_ADC_PIN0_PORT AO_ADC_SENSE_PAD_0_PORT
219 #define AO_ADC_PIN0_PIN AO_ADC_SENSE_PAD_0_PIN
221 #define AO_ADC_PIN1_PORT AO_ADC_SENSE_PAD_1_PORT
222 #define AO_ADC_PIN1_PIN AO_ADC_SENSE_PAD_1_PIN
224 #define AO_ADC_PIN2_PORT AO_ADC_SENSE_PAD_2_PORT
225 #define AO_ADC_PIN2_PIN AO_ADC_SENSE_PAD_2_PIN
227 #define AO_ADC_PIN3_PORT AO_ADC_SENSE_PAD_3_PORT
228 #define AO_ADC_PIN3_PIN AO_ADC_SENSE_PAD_3_PIN
230 #define AO_ADC_PIN4_PORT AO_ADC_SENSE_PAD_4_PORT
231 #define AO_ADC_PIN4_PIN AO_ADC_SENSE_PAD_4_PIN
233 #define AO_ADC_PIN5_PORT AO_ADC_SENSE_PAD_5_PORT
234 #define AO_ADC_PIN5_PIN AO_ADC_SENSE_PAD_5_PIN
236 #define AO_ADC_PIN6_PORT AO_ADC_SENSE_PAD_6_PORT
237 #define AO_ADC_PIN6_PIN AO_ADC_SENSE_PAD_6_PIN
239 #define AO_ADC_PIN7_PORT AO_ADC_SENSE_PAD_7_PORT
240 #define AO_ADC_PIN7_PIN AO_ADC_SENSE_PAD_7_PIN
242 #define AO_ADC_PIN8_PORT AO_ADC_PYRO_PORT
243 #define AO_ADC_PIN8_PIN AO_ADC_PYRO_PIN
245 #define AO_ADC_PIN9_PORT AO_ADC_BATT_PORT
246 #define AO_ADC_PIN9_PIN AO_ADC_BATT_PIN
248 #define AO_PAD_ALL_CHANNELS (0xff)
250 /* test these values with real igniters */
251 #define AO_PAD_RELAY_CLOSED 3524
252 #define AO_PAD_NO_IGNITER 16904
253 #define AO_PAD_GOOD_IGNITER 22514
255 #define AO_ADC_FIRST_PIN 0
257 #define AO_NUM_ADC 10
259 #define AO_ADC_SQ1 AO_ADC_SENSE_PAD_0
260 #define AO_ADC_SQ2 AO_ADC_SENSE_PAD_1
261 #define AO_ADC_SQ3 AO_ADC_SENSE_PAD_2
262 #define AO_ADC_SQ4 AO_ADC_SENSE_PAD_3
263 #define AO_ADC_SQ5 AO_ADC_SENSE_PAD_4
264 #define AO_ADC_SQ6 AO_ADC_SENSE_PAD_5
265 #define AO_ADC_SQ7 AO_ADC_SENSE_PAD_6
266 #define AO_ADC_SQ8 AO_ADC_SENSE_PAD_7
267 #define AO_ADC_SQ9 AO_ADC_PYRO
268 #define AO_ADC_SQ10 AO_ADC_BATT
270 #define AO_ADC_REFERENCE_DV 33
272 #define AO_ADC_RCC_AHBENR ((1 << STM_RCC_AHBENR_GPIOAEN) | \
273 (1 << STM_RCC_AHBENR_GPIOBEN) | \
274 (1 << STM_RCC_AHBENR_GPIOCEN))
277 #define AO_PAD_R_V_BATT_BATT_SENSE 200
278 #define AO_PAD_R_BATT_SENSE_GND 22
280 #define AO_PAD_R_V_BATT_V_PYRO 200
281 #define AO_PAD_R_V_PYRO_PYRO_SENSE 200
282 #define AO_PAD_R_PYRO_SENSE_GND 22
284 #undef AO_PAD_R_V_PYRO_IGNITER
285 #define AO_PAD_R_IGNITER_IGNITER_SENSE 200
286 #define AO_PAD_R_IGNITER_SENSE_GND 22
288 #define HAS_ADC_TEMP 0
291 int16_t sense[AO_PAD_NUM];
296 #define AO_ADC_DUMP(p) \
297 printf ("tick: %5u " \
298 "0: %5d 1: %5d 2: %5d 3: %5d " \
299 "4: %5d 5: %5d 6: %5d 7: %5d " \
300 "pyro: %5d batt: %5d\n", \
313 #endif /* _AO_PINS_H_ */