2 * Copyright © 2010 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
23 #define HAS_RADIO_RATE 1
24 #define HAS_TELEMETRY 0
29 #define HAS_SERIAL_1 0
35 #define USE_INTERNAL_FLASH 1
36 #define IGNITE_ON_P0 0
37 #define PACKET_HAS_MASTER 0
38 #define PACKET_HAS_SLAVE 0
39 #define AO_DATA_RING 32
40 #define USE_EEPROM_CONFIG 1
41 #define USE_STORAGE_CONFIG 0
44 /* 8MHz High speed external crystal */
45 #define AO_HSE 8000000
47 /* PLLVCO = 96MHz (so that USB will work) */
49 #define AO_RCC_CFGR_PLLMUL (STM_RCC_CFGR_PLLMUL_12)
51 #define AO_CC1200_FOSC 40000000
53 /* SYSCLK = 32MHz (no need to go faster than CPU) */
55 #define AO_RCC_CFGR_PLLDIV (STM_RCC_CFGR_PLLDIV_3)
57 /* HCLK = 32MHz (CPU clock) */
58 #define AO_AHB_PRESCALER 1
59 #define AO_RCC_CFGR_HPRE_DIV STM_RCC_CFGR_HPRE_DIV_1
61 /* Run APB1 at 16MHz (HCLK/2) */
62 #define AO_APB1_PRESCALER 2
63 #define AO_RCC_CFGR_PPRE1_DIV STM_RCC_CFGR_PPRE2_DIV_2
65 /* Run APB2 at 16MHz (HCLK/2) */
66 #define AO_APB2_PRESCALER 2
67 #define AO_RCC_CFGR_PPRE2_DIV STM_RCC_CFGR_PPRE2_DIV_2
70 #define SPI_1_PA5_PA6_PA7 0
71 #define SPI_1_PB3_PB4_PB5 0
72 #define SPI_1_PE13_PE14_PE15 1
73 #define SPI_1_GPIO (&stm_gpioe)
77 #define SPI_1_OSPEEDR STM_OSPEEDR_10MHz
80 #define SPI_2_PB13_PB14_PB15 0
81 #define SPI_2_PD1_PD3_PD4 0
87 #define PACKET_HAS_SLAVE 0
88 #define PACKET_HAS_MASTER 0
90 #define FAST_TIMER_FREQ 10000 /* .1ms for debouncing */
93 * Radio is a cc1200 connected via SPI
96 #define AO_RADIO_CAL_DEFAULT 5695733
98 #define AO_CC1200_SPI_CS_PORT (&stm_gpioe)
99 #define AO_CC1200_SPI_CS_PIN 11
100 #define AO_CC1200_SPI_BUS AO_SPI_1_PE13_PE14_PE15
101 #define AO_CC1200_SPI stm_spi1
102 #define AO_CC1200_SPI_SPEED AO_SPI_SPEED_FAST
104 #define AO_CC1200_INT_PORT (&stm_gpioe)
105 #define AO_CC1200_INT_PIN (12)
107 #define AO_CC1200_INT_GPIO 2
108 #define AO_CC1200_INT_GPIO_IOCFG CC1200_IOCFG2
111 #define LED_TYPE uint16_t
113 /* Continuity leds 1-8 */
114 #define LED_0_PORT (&stm_gpiob)
116 #define LED_1_PORT (&stm_gpiob)
118 #define LED_2_PORT (&stm_gpiob)
120 #define LED_3_PORT (&stm_gpiob)
122 #define LED_4_PORT (&stm_gpioc)
124 #define LED_5_PORT (&stm_gpioa)
126 #define LED_6_PORT (&stm_gpioa)
128 #define LED_7_PORT (&stm_gpioa)
131 #define AO_LED_CONTINUITY(c) (1 << (c))
132 #define AO_LED_CONTINUITY_MASK (0xff)
135 #define LED_8_PORT (&stm_gpioe)
138 #define LED_PIN_ARMED 8
140 /* RF good/marginal/poor */
141 #define LED_9_PORT (&stm_gpioe)
143 #define LED_10_PORT (&stm_gpioe)
145 #define LED_11_PORT (&stm_gpioe)
148 #define AO_LED_ARMED AO_LED_8
149 #define AO_LED_GREEN AO_LED_9
150 #define AO_LED_AMBER AO_LED_10
151 #define AO_LED_RED AO_LED_11
155 #define AO_SIREN_PORT (&stm_gpiod)
156 #define AO_SIREN_PIN 10
160 #define AO_STROBE_PORT (&stm_gpiod)
161 #define AO_STROBE_PIN 11
163 /* Pad selector is on PD0-7 */
165 #define HAS_FIXED_PAD_BOX 1
166 #define AO_PAD_SELECTOR_PORT (&stm_gpiod)
167 #define AO_PAD_SELECTOR_PINS (0xff)
169 #define SPI_CONST 0x00
172 #define AO_PAD_PORT_0 (&stm_gpiod)
173 #define AO_PAD_PORT_1 (&stm_gpiob)
175 #define AO_PAD_PIN_0 9
176 #define AO_PAD_0_PORT (&stm_gpiod)
177 #define AO_ADC_SENSE_PAD_0 3
178 #define AO_ADC_SENSE_PAD_0_PORT (&stm_gpioa)
179 #define AO_ADC_SENSE_PAD_0_PIN 3
181 #define AO_PAD_PIN_1 8
182 #define AO_PAD_1_PORT (&stm_gpiod)
183 #define AO_ADC_SENSE_PAD_1 2
184 #define AO_ADC_SENSE_PAD_1_PORT (&stm_gpioa)
185 #define AO_ADC_SENSE_PAD_1_PIN 2
187 #define AO_PAD_PIN_2 15
188 #define AO_PAD_2_PORT (&stm_gpiob)
189 #define AO_ADC_SENSE_PAD_2 1
190 #define AO_ADC_SENSE_PAD_2_PORT (&stm_gpioa)
191 #define AO_ADC_SENSE_PAD_2_PIN 1
193 #define AO_PAD_PIN_3 14
194 #define AO_PAD_3_PORT (&stm_gpiob)
195 #define AO_ADC_SENSE_PAD_3 0
196 #define AO_ADC_SENSE_PAD_3_PORT (&stm_gpioa)
197 #define AO_ADC_SENSE_PAD_3_PIN 0
199 #define AO_PAD_PIN_4 12
200 #define AO_PAD_4_PORT (&stm_gpiod)
201 #define AO_ADC_SENSE_PAD_4 7
202 #define AO_ADC_SENSE_PAD_4_PORT (&stm_gpioa)
203 #define AO_ADC_SENSE_PAD_4_PIN 7
205 #define AO_PAD_PIN_5 13
206 #define AO_PAD_5_PORT (&stm_gpiod)
207 #define AO_ADC_SENSE_PAD_5 6
208 #define AO_ADC_SENSE_PAD_5_PORT (&stm_gpioa)
209 #define AO_ADC_SENSE_PAD_5_PIN 6
211 #define AO_PAD_PIN_6 14
212 #define AO_PAD_6_PORT (&stm_gpiod)
213 #define AO_ADC_SENSE_PAD_6 5
214 #define AO_ADC_SENSE_PAD_6_PORT (&stm_gpioa)
215 #define AO_ADC_SENSE_PAD_6_PIN 5
217 #define AO_PAD_PIN_7 15
218 #define AO_PAD_7_PORT (&stm_gpiod)
219 #define AO_ADC_SENSE_PAD_7 4
220 #define AO_ADC_SENSE_PAD_7_PORT (&stm_gpioa)
221 #define AO_ADC_SENSE_PAD_7_PIN 4
223 #define AO_ADC_PYRO 8
224 #define AO_ADC_PYRO_PORT (&stm_gpiob)
225 #define AO_ADC_PYRO_PIN 0
227 #define AO_ADC_BATT 15
228 #define AO_ADC_BATT_PORT (&stm_gpioc)
229 #define AO_ADC_BATT_PIN 5
231 #define AO_ADC_PIN0_PORT AO_ADC_SENSE_PAD_0_PORT
232 #define AO_ADC_PIN0_PIN AO_ADC_SENSE_PAD_0_PIN
234 #define AO_ADC_PIN1_PORT AO_ADC_SENSE_PAD_1_PORT
235 #define AO_ADC_PIN1_PIN AO_ADC_SENSE_PAD_1_PIN
237 #define AO_ADC_PIN2_PORT AO_ADC_SENSE_PAD_2_PORT
238 #define AO_ADC_PIN2_PIN AO_ADC_SENSE_PAD_2_PIN
240 #define AO_ADC_PIN3_PORT AO_ADC_SENSE_PAD_3_PORT
241 #define AO_ADC_PIN3_PIN AO_ADC_SENSE_PAD_3_PIN
243 #define AO_ADC_PIN4_PORT AO_ADC_SENSE_PAD_4_PORT
244 #define AO_ADC_PIN4_PIN AO_ADC_SENSE_PAD_4_PIN
246 #define AO_ADC_PIN5_PORT AO_ADC_SENSE_PAD_5_PORT
247 #define AO_ADC_PIN5_PIN AO_ADC_SENSE_PAD_5_PIN
249 #define AO_ADC_PIN6_PORT AO_ADC_SENSE_PAD_6_PORT
250 #define AO_ADC_PIN6_PIN AO_ADC_SENSE_PAD_6_PIN
252 #define AO_ADC_PIN7_PORT AO_ADC_SENSE_PAD_7_PORT
253 #define AO_ADC_PIN7_PIN AO_ADC_SENSE_PAD_7_PIN
255 #define AO_ADC_PIN8_PORT AO_ADC_PYRO_PORT
256 #define AO_ADC_PIN8_PIN AO_ADC_PYRO_PIN
258 #define AO_ADC_PIN9_PORT AO_ADC_BATT_PORT
259 #define AO_ADC_PIN9_PIN AO_ADC_BATT_PIN
261 #define AO_PAD_ALL_CHANNELS (0xff)
263 /* test these values with real igniters */
264 #define AO_PAD_RELAY_CLOSED 3524
265 #define AO_PAD_NO_IGNITER 16904
266 #define AO_PAD_GOOD_IGNITER 22514
268 #define AO_ADC_FIRST_PIN 0
270 #define AO_NUM_ADC 10
272 #define AO_ADC_SQ1 AO_ADC_SENSE_PAD_0
273 #define AO_ADC_SQ2 AO_ADC_SENSE_PAD_1
274 #define AO_ADC_SQ3 AO_ADC_SENSE_PAD_2
275 #define AO_ADC_SQ4 AO_ADC_SENSE_PAD_3
276 #define AO_ADC_SQ5 AO_ADC_SENSE_PAD_4
277 #define AO_ADC_SQ6 AO_ADC_SENSE_PAD_5
278 #define AO_ADC_SQ7 AO_ADC_SENSE_PAD_6
279 #define AO_ADC_SQ8 AO_ADC_SENSE_PAD_7
280 #define AO_ADC_SQ9 AO_ADC_PYRO
281 #define AO_ADC_SQ10 AO_ADC_BATT
283 #define AO_ADC_REFERENCE_DV 33
285 #define AO_ADC_RCC_AHBENR ((1 << STM_RCC_AHBENR_GPIOAEN) | \
286 (1 << STM_RCC_AHBENR_GPIOBEN) | \
287 (1 << STM_RCC_AHBENR_GPIOCEN))
290 #define AO_PAD_R_V_BATT_BATT_SENSE 200
291 #define AO_PAD_R_BATT_SENSE_GND 22
293 #define AO_PAD_R_V_BATT_V_PYRO 200
294 #define AO_PAD_R_V_PYRO_PYRO_SENSE 200
295 #define AO_PAD_R_PYRO_SENSE_GND 22
297 #undef AO_PAD_R_V_PYRO_IGNITER
298 #define AO_PAD_R_IGNITER_IGNITER_SENSE 200
299 #define AO_PAD_R_IGNITER_SENSE_GND 22
301 #define HAS_ADC_TEMP 0
304 int16_t sense[AO_PAD_NUM];
309 #define AO_ADC_DUMP(p) \
310 printf ("tick: %5u " \
311 "0: %5d 1: %5d 2: %5d 3: %5d " \
312 "4: %5d 5: %5d 6: %5d 7: %5d " \
313 "pyro: %5d batt: %5d\n", \
326 #endif /* _AO_PINS_H_ */